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path: root/drivers/gpu/drm/radeon/radeon_device.c
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Diffstat (limited to 'drivers/gpu/drm/radeon/radeon_device.c')
-rw-r--r--drivers/gpu/drm/radeon/radeon_device.c59
1 files changed, 37 insertions, 22 deletions
diff --git a/drivers/gpu/drm/radeon/radeon_device.c b/drivers/gpu/drm/radeon/radeon_device.c
index f97563db4e59..a162ade74b7f 100644
--- a/drivers/gpu/drm/radeon/radeon_device.c
+++ b/drivers/gpu/drm/radeon/radeon_device.c
@@ -48,6 +48,8 @@ static void radeon_surface_init(struct radeon_device *rdev)
48 i * (RADEON_SURFACE1_INFO - RADEON_SURFACE0_INFO), 48 i * (RADEON_SURFACE1_INFO - RADEON_SURFACE0_INFO),
49 0); 49 0);
50 } 50 }
51 /* enable surfaces */
52 WREG32(RADEON_SURFACE_CNTL, 0);
51 } 53 }
52} 54}
53 55
@@ -119,7 +121,7 @@ int radeon_mc_setup(struct radeon_device *rdev)
119 if (rdev->mc.vram_location != 0xFFFFFFFFUL) { 121 if (rdev->mc.vram_location != 0xFFFFFFFFUL) {
120 /* vram location was already setup try to put gtt after 122 /* vram location was already setup try to put gtt after
121 * if it fits */ 123 * if it fits */
122 tmp = rdev->mc.vram_location + rdev->mc.vram_size; 124 tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size;
123 tmp = (tmp + rdev->mc.gtt_size - 1) & ~(rdev->mc.gtt_size - 1); 125 tmp = (tmp + rdev->mc.gtt_size - 1) & ~(rdev->mc.gtt_size - 1);
124 if ((0xFFFFFFFFUL - tmp) >= rdev->mc.gtt_size) { 126 if ((0xFFFFFFFFUL - tmp) >= rdev->mc.gtt_size) {
125 rdev->mc.gtt_location = tmp; 127 rdev->mc.gtt_location = tmp;
@@ -134,13 +136,13 @@ int radeon_mc_setup(struct radeon_device *rdev)
134 } else if (rdev->mc.gtt_location != 0xFFFFFFFFUL) { 136 } else if (rdev->mc.gtt_location != 0xFFFFFFFFUL) {
135 /* gtt location was already setup try to put vram before 137 /* gtt location was already setup try to put vram before
136 * if it fits */ 138 * if it fits */
137 if (rdev->mc.vram_size < rdev->mc.gtt_location) { 139 if (rdev->mc.mc_vram_size < rdev->mc.gtt_location) {
138 rdev->mc.vram_location = 0; 140 rdev->mc.vram_location = 0;
139 } else { 141 } else {
140 tmp = rdev->mc.gtt_location + rdev->mc.gtt_size; 142 tmp = rdev->mc.gtt_location + rdev->mc.gtt_size;
141 tmp += (rdev->mc.vram_size - 1); 143 tmp += (rdev->mc.mc_vram_size - 1);
142 tmp &= ~(rdev->mc.vram_size - 1); 144 tmp &= ~(rdev->mc.mc_vram_size - 1);
143 if ((0xFFFFFFFFUL - tmp) >= rdev->mc.vram_size) { 145 if ((0xFFFFFFFFUL - tmp) >= rdev->mc.mc_vram_size) {
144 rdev->mc.vram_location = tmp; 146 rdev->mc.vram_location = tmp;
145 } else { 147 } else {
146 printk(KERN_ERR "[drm] vram too big to fit " 148 printk(KERN_ERR "[drm] vram too big to fit "
@@ -150,12 +152,14 @@ int radeon_mc_setup(struct radeon_device *rdev)
150 } 152 }
151 } else { 153 } else {
152 rdev->mc.vram_location = 0; 154 rdev->mc.vram_location = 0;
153 rdev->mc.gtt_location = rdev->mc.vram_size; 155 rdev->mc.gtt_location = rdev->mc.mc_vram_size;
154 } 156 }
155 DRM_INFO("radeon: VRAM %uM\n", rdev->mc.vram_size >> 20); 157 DRM_INFO("radeon: VRAM %uM\n", rdev->mc.real_vram_size >> 20);
156 DRM_INFO("radeon: VRAM from 0x%08X to 0x%08X\n", 158 DRM_INFO("radeon: VRAM from 0x%08X to 0x%08X\n",
157 rdev->mc.vram_location, 159 rdev->mc.vram_location,
158 rdev->mc.vram_location + rdev->mc.vram_size - 1); 160 rdev->mc.vram_location + rdev->mc.mc_vram_size - 1);
161 if (rdev->mc.real_vram_size != rdev->mc.mc_vram_size)
162 DRM_INFO("radeon: VRAM less than aperture workaround enabled\n");
159 DRM_INFO("radeon: GTT %uM\n", rdev->mc.gtt_size >> 20); 163 DRM_INFO("radeon: GTT %uM\n", rdev->mc.gtt_size >> 20);
160 DRM_INFO("radeon: GTT from 0x%08X to 0x%08X\n", 164 DRM_INFO("radeon: GTT from 0x%08X to 0x%08X\n",
161 rdev->mc.gtt_location, 165 rdev->mc.gtt_location,
@@ -450,6 +454,7 @@ int radeon_device_init(struct radeon_device *rdev,
450 uint32_t flags) 454 uint32_t flags)
451{ 455{
452 int r, ret; 456 int r, ret;
457 int dma_bits;
453 458
454 DRM_INFO("radeon: Initializing kernel modesetting.\n"); 459 DRM_INFO("radeon: Initializing kernel modesetting.\n");
455 rdev->shutdown = false; 460 rdev->shutdown = false;
@@ -492,8 +497,20 @@ int radeon_device_init(struct radeon_device *rdev,
492 return r; 497 return r;
493 } 498 }
494 499
495 /* Report DMA addressing limitation */ 500 /* set DMA mask + need_dma32 flags.
496 r = pci_set_dma_mask(rdev->pdev, DMA_BIT_MASK(32)); 501 * PCIE - can handle 40-bits.
502 * IGP - can handle 40-bits (in theory)
503 * AGP - generally dma32 is safest
504 * PCI - only dma32
505 */
506 rdev->need_dma32 = false;
507 if (rdev->flags & RADEON_IS_AGP)
508 rdev->need_dma32 = true;
509 if (rdev->flags & RADEON_IS_PCI)
510 rdev->need_dma32 = true;
511
512 dma_bits = rdev->need_dma32 ? 32 : 40;
513 r = pci_set_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits));
497 if (r) { 514 if (r) {
498 printk(KERN_WARNING "radeon: No suitable DMA available.\n"); 515 printk(KERN_WARNING "radeon: No suitable DMA available.\n");
499 } 516 }
@@ -546,27 +563,22 @@ int radeon_device_init(struct radeon_device *rdev,
546 radeon_combios_asic_init(rdev->ddev); 563 radeon_combios_asic_init(rdev->ddev);
547 } 564 }
548 } 565 }
566 /* Initialize clocks */
567 r = radeon_clocks_init(rdev);
568 if (r) {
569 return r;
570 }
549 /* Get vram informations */ 571 /* Get vram informations */
550 radeon_vram_info(rdev); 572 radeon_vram_info(rdev);
551 /* Device is severly broken if aper size > vram size. 573
552 * for RN50/M6/M7 - Novell bug 204882 ?
553 */
554 if (rdev->mc.vram_size < rdev->mc.aper_size) {
555 rdev->mc.aper_size = rdev->mc.vram_size;
556 }
557 /* Add an MTRR for the VRAM */ 574 /* Add an MTRR for the VRAM */
558 rdev->mc.vram_mtrr = mtrr_add(rdev->mc.aper_base, rdev->mc.aper_size, 575 rdev->mc.vram_mtrr = mtrr_add(rdev->mc.aper_base, rdev->mc.aper_size,
559 MTRR_TYPE_WRCOMB, 1); 576 MTRR_TYPE_WRCOMB, 1);
560 DRM_INFO("Detected VRAM RAM=%uM, BAR=%uM\n", 577 DRM_INFO("Detected VRAM RAM=%uM, BAR=%uM\n",
561 rdev->mc.vram_size >> 20, 578 rdev->mc.real_vram_size >> 20,
562 (unsigned)rdev->mc.aper_size >> 20); 579 (unsigned)rdev->mc.aper_size >> 20);
563 DRM_INFO("RAM width %dbits %cDR\n", 580 DRM_INFO("RAM width %dbits %cDR\n",
564 rdev->mc.vram_width, rdev->mc.vram_is_ddr ? 'D' : 'S'); 581 rdev->mc.vram_width, rdev->mc.vram_is_ddr ? 'D' : 'S');
565 /* Initialize clocks */
566 r = radeon_clocks_init(rdev);
567 if (r) {
568 return r;
569 }
570 /* Initialize memory controller (also test AGP) */ 582 /* Initialize memory controller (also test AGP) */
571 r = radeon_mc_init(rdev); 583 r = radeon_mc_init(rdev);
572 if (r) { 584 if (r) {
@@ -626,6 +638,9 @@ int radeon_device_init(struct radeon_device *rdev,
626 if (!ret) { 638 if (!ret) {
627 DRM_INFO("radeon: kernel modesetting successfully initialized.\n"); 639 DRM_INFO("radeon: kernel modesetting successfully initialized.\n");
628 } 640 }
641 if (radeon_testing) {
642 radeon_test_moves(rdev);
643 }
629 if (radeon_benchmarking) { 644 if (radeon_benchmarking) {
630 radeon_benchmark(rdev); 645 radeon_benchmark(rdev);
631 } 646 }