1 files changed, 157 insertions, 15 deletions

diff --git a/drivers/gpu/drm/radeon/radeon_asic.h b/drivers/gpu/drm/radeon/radeon_asic.h
index 05ee1aeac3fd..d3a157b2bcb7 100644
--- a/drivers/gpu/drm/radeon/radeon_asic.h
+++ b/drivers/gpu/drm/radeon/radeon_asic.h
@@ -43,7 +43,7 @@ void radeon_atom_set_memory_clock(struct radeon_device *rdev, uint32_t mem_clock
 void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
 
 /*
- * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280
+ * r100,rv100,rs100,rv200,rs200
  */
 extern int r100_init(struct radeon_device *rdev);
 extern void r100_fini(struct radeon_device *rdev);
@@ -108,6 +108,52 @@ static struct radeon_asic r100_asic = {
         .set_engine_clock = &radeon_legacy_set_engine_clock,
         .get_memory_clock = &radeon_legacy_get_memory_clock,
         .set_memory_clock = NULL,
+        .get_pcie_lanes = NULL,
+        .set_pcie_lanes = NULL,
+        .set_clock_gating = &radeon_legacy_set_clock_gating,
+        .set_surface_reg = r100_set_surface_reg,
+        .clear_surface_reg = r100_clear_surface_reg,
+        .bandwidth_update = &r100_bandwidth_update,
+        .hpd_init = &r100_hpd_init,
+        .hpd_fini = &r100_hpd_fini,
+        .hpd_sense = &r100_hpd_sense,
+        .hpd_set_polarity = &r100_hpd_set_polarity,
+        .ioctl_wait_idle = NULL,
+};
+
+/*
+ * r200,rv250,rs300,rv280
+ */
+extern int r200_copy_dma(struct radeon_device *rdev,
+                        uint64_t src_offset,
+                        uint64_t dst_offset,
+                        unsigned num_pages,
+                        struct radeon_fence *fence);
+static struct radeon_asic r200_asic = {
+        .init = &r100_init,
+        .fini = &r100_fini,
+        .suspend = &r100_suspend,
+        .resume = &r100_resume,
+        .vga_set_state = &r100_vga_set_state,
+        .gpu_reset = &r100_gpu_reset,
+        .gart_tlb_flush = &r100_pci_gart_tlb_flush,
+        .gart_set_page = &r100_pci_gart_set_page,
+        .cp_commit = &r100_cp_commit,
+        .ring_start = &r100_ring_start,
+        .ring_test = &r100_ring_test,
+        .ring_ib_execute = &r100_ring_ib_execute,
+        .irq_set = &r100_irq_set,
+        .irq_process = &r100_irq_process,
+        .get_vblank_counter = &r100_get_vblank_counter,
+        .fence_ring_emit = &r100_fence_ring_emit,
+        .cs_parse = &r100_cs_parse,
+        .copy_blit = &r100_copy_blit,
+        .copy_dma = &r200_copy_dma,
+        .copy = &r100_copy_blit,
+        .get_engine_clock = &radeon_legacy_get_engine_clock,
+        .set_engine_clock = &radeon_legacy_set_engine_clock,
+        .get_memory_clock = &radeon_legacy_get_memory_clock,
+        .set_memory_clock = NULL,
         .set_pcie_lanes = NULL,
         .set_clock_gating = &radeon_legacy_set_clock_gating,
         .set_surface_reg = r100_set_surface_reg,
@@ -138,11 +184,8 @@ extern int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t
 extern uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg);
 extern void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
 extern void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes);
-extern int r300_copy_dma(struct radeon_device *rdev,
-                        uint64_t src_offset,
-                        uint64_t dst_offset,
-                        unsigned num_pages,
-                        struct radeon_fence *fence);
+extern int rv370_get_pcie_lanes(struct radeon_device *rdev);
+
 static struct radeon_asic r300_asic = {
         .init = &r300_init,
         .fini = &r300_fini,
@@ -162,7 +205,46 @@ static struct radeon_asic r300_asic = {
         .fence_ring_emit = &r300_fence_ring_emit,
         .cs_parse = &r300_cs_parse,
         .copy_blit = &r100_copy_blit,
-        .copy_dma = &r300_copy_dma,
+        .copy_dma = &r200_copy_dma,
+        .copy = &r100_copy_blit,
+        .get_engine_clock = &radeon_legacy_get_engine_clock,
+        .set_engine_clock = &radeon_legacy_set_engine_clock,
+        .get_memory_clock = &radeon_legacy_get_memory_clock,
+        .set_memory_clock = NULL,
+        .get_pcie_lanes = &rv370_get_pcie_lanes,
+        .set_pcie_lanes = &rv370_set_pcie_lanes,
+        .set_clock_gating = &radeon_legacy_set_clock_gating,
+        .set_surface_reg = r100_set_surface_reg,
+        .clear_surface_reg = r100_clear_surface_reg,
+        .bandwidth_update = &r100_bandwidth_update,
+        .hpd_init = &r100_hpd_init,
+        .hpd_fini = &r100_hpd_fini,
+        .hpd_sense = &r100_hpd_sense,
+        .hpd_set_polarity = &r100_hpd_set_polarity,
+        .ioctl_wait_idle = NULL,
+};
+
+
+static struct radeon_asic r300_asic_pcie = {
+        .init = &r300_init,
+        .fini = &r300_fini,
+        .suspend = &r300_suspend,
+        .resume = &r300_resume,
+        .vga_set_state = &r100_vga_set_state,
+        .gpu_reset = &r300_gpu_reset,
+        .gart_tlb_flush = &rv370_pcie_gart_tlb_flush,
+        .gart_set_page = &rv370_pcie_gart_set_page,
+        .cp_commit = &r100_cp_commit,
+        .ring_start = &r300_ring_start,
+        .ring_test = &r100_ring_test,
+        .ring_ib_execute = &r100_ring_ib_execute,
+        .irq_set = &r100_irq_set,
+        .irq_process = &r100_irq_process,
+        .get_vblank_counter = &r100_get_vblank_counter,
+        .fence_ring_emit = &r300_fence_ring_emit,
+        .cs_parse = &r300_cs_parse,
+        .copy_blit = &r100_copy_blit,
+        .copy_dma = &r200_copy_dma,
         .copy = &r100_copy_blit,
         .get_engine_clock = &radeon_legacy_get_engine_clock,
         .set_engine_clock = &radeon_legacy_set_engine_clock,
@@ -206,12 +288,13 @@ static struct radeon_asic r420_asic = {
         .fence_ring_emit = &r300_fence_ring_emit,
         .cs_parse = &r300_cs_parse,
         .copy_blit = &r100_copy_blit,
-        .copy_dma = &r300_copy_dma,
+        .copy_dma = &r200_copy_dma,
         .copy = &r100_copy_blit,
         .get_engine_clock = &radeon_atom_get_engine_clock,
         .set_engine_clock = &radeon_atom_set_engine_clock,
         .get_memory_clock = &radeon_atom_get_memory_clock,
         .set_memory_clock = &radeon_atom_set_memory_clock,
+        .get_pcie_lanes = &rv370_get_pcie_lanes,
         .set_pcie_lanes = &rv370_set_pcie_lanes,
         .set_clock_gating = &radeon_atom_set_clock_gating,
         .set_surface_reg = r100_set_surface_reg,
@@ -255,12 +338,13 @@ static struct radeon_asic rs400_asic = {
         .fence_ring_emit = &r300_fence_ring_emit,
         .cs_parse = &r300_cs_parse,
         .copy_blit = &r100_copy_blit,
-        .copy_dma = &r300_copy_dma,
+        .copy_dma = &r200_copy_dma,
         .copy = &r100_copy_blit,
         .get_engine_clock = &radeon_legacy_get_engine_clock,
         .set_engine_clock = &radeon_legacy_set_engine_clock,
         .get_memory_clock = &radeon_legacy_get_memory_clock,
         .set_memory_clock = NULL,
+        .get_pcie_lanes = NULL,
         .set_pcie_lanes = NULL,
         .set_clock_gating = &radeon_legacy_set_clock_gating,
         .set_surface_reg = r100_set_surface_reg,
@@ -314,14 +398,17 @@ static struct radeon_asic rs600_asic = {
         .fence_ring_emit = &r300_fence_ring_emit,
         .cs_parse = &r300_cs_parse,
         .copy_blit = &r100_copy_blit,
-        .copy_dma = &r300_copy_dma,
+        .copy_dma = &r200_copy_dma,
         .copy = &r100_copy_blit,
         .get_engine_clock = &radeon_atom_get_engine_clock,
         .set_engine_clock = &radeon_atom_set_engine_clock,
         .get_memory_clock = &radeon_atom_get_memory_clock,
         .set_memory_clock = &radeon_atom_set_memory_clock,
+        .get_pcie_lanes = NULL,
         .set_pcie_lanes = NULL,
         .set_clock_gating = &radeon_atom_set_clock_gating,
+        .set_surface_reg = r100_set_surface_reg,
+        .clear_surface_reg = r100_clear_surface_reg,
         .bandwidth_update = &rs600_bandwidth_update,
         .hpd_init = &rs600_hpd_init,
         .hpd_fini = &rs600_hpd_fini,
@@ -360,12 +447,13 @@ static struct radeon_asic rs690_asic = {
         .fence_ring_emit = &r300_fence_ring_emit,
         .cs_parse = &r300_cs_parse,
         .copy_blit = &r100_copy_blit,
-        .copy_dma = &r300_copy_dma,
-        .copy = &r300_copy_dma,
+        .copy_dma = &r200_copy_dma,
+        .copy = &r200_copy_dma,
         .get_engine_clock = &radeon_atom_get_engine_clock,
         .set_engine_clock = &radeon_atom_set_engine_clock,
         .get_memory_clock = &radeon_atom_get_memory_clock,
         .set_memory_clock = &radeon_atom_set_memory_clock,
+        .get_pcie_lanes = NULL,
         .set_pcie_lanes = NULL,
         .set_clock_gating = &radeon_atom_set_clock_gating,
         .set_surface_reg = r100_set_surface_reg,
@@ -412,12 +500,13 @@ static struct radeon_asic rv515_asic = {
         .fence_ring_emit = &r300_fence_ring_emit,
         .cs_parse = &r300_cs_parse,
         .copy_blit = &r100_copy_blit,
-        .copy_dma = &r300_copy_dma,
+        .copy_dma = &r200_copy_dma,
         .copy = &r100_copy_blit,
         .get_engine_clock = &radeon_atom_get_engine_clock,
         .set_engine_clock = &radeon_atom_set_engine_clock,
         .get_memory_clock = &radeon_atom_get_memory_clock,
         .set_memory_clock = &radeon_atom_set_memory_clock,
+        .get_pcie_lanes = &rv370_get_pcie_lanes,
         .set_pcie_lanes = &rv370_set_pcie_lanes,
         .set_clock_gating = &radeon_atom_set_clock_gating,
         .set_surface_reg = r100_set_surface_reg,
@@ -455,12 +544,13 @@ static struct radeon_asic r520_asic = {
         .fence_ring_emit = &r300_fence_ring_emit,
         .cs_parse = &r300_cs_parse,
         .copy_blit = &r100_copy_blit,
-        .copy_dma = &r300_copy_dma,
+        .copy_dma = &r200_copy_dma,
         .copy = &r100_copy_blit,
         .get_engine_clock = &radeon_atom_get_engine_clock,
         .set_engine_clock = &radeon_atom_set_engine_clock,
         .get_memory_clock = &radeon_atom_get_memory_clock,
         .set_memory_clock = &radeon_atom_set_memory_clock,
+        .get_pcie_lanes = &rv370_get_pcie_lanes,
         .set_pcie_lanes = &rv370_set_pcie_lanes,
         .set_clock_gating = &radeon_atom_set_clock_gating,
         .set_surface_reg = r100_set_surface_reg,
@@ -538,8 +628,9 @@ static struct radeon_asic r600_asic = {
         .set_engine_clock = &radeon_atom_set_engine_clock,
         .get_memory_clock = &radeon_atom_get_memory_clock,
         .set_memory_clock = &radeon_atom_set_memory_clock,
+        .get_pcie_lanes = &rv370_get_pcie_lanes,
         .set_pcie_lanes = NULL,
-        .set_clock_gating = &radeon_atom_set_clock_gating,
+        .set_clock_gating = NULL,
         .set_surface_reg = r600_set_surface_reg,
         .clear_surface_reg = r600_clear_surface_reg,
         .bandwidth_update = &rv515_bandwidth_update,
@@ -583,6 +674,7 @@ static struct radeon_asic rv770_asic = {
         .set_engine_clock = &radeon_atom_set_engine_clock,
         .get_memory_clock = &radeon_atom_get_memory_clock,
         .set_memory_clock = &radeon_atom_set_memory_clock,
+        .get_pcie_lanes = &rv370_get_pcie_lanes,
         .set_pcie_lanes = NULL,
         .set_clock_gating = &radeon_atom_set_clock_gating,
         .set_surface_reg = r600_set_surface_reg,
@@ -595,4 +687,54 @@ static struct radeon_asic rv770_asic = {
         .ioctl_wait_idle = r600_ioctl_wait_idle,
 };
 
+/*
+ * evergreen
+ */
+int evergreen_init(struct radeon_device *rdev);
+void evergreen_fini(struct radeon_device *rdev);
+int evergreen_suspend(struct radeon_device *rdev);
+int evergreen_resume(struct radeon_device *rdev);
+int evergreen_gpu_reset(struct radeon_device *rdev);
+void evergreen_bandwidth_update(struct radeon_device *rdev);
+void evergreen_hpd_init(struct radeon_device *rdev);
+void evergreen_hpd_fini(struct radeon_device *rdev);
+bool evergreen_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
+void evergreen_hpd_set_polarity(struct radeon_device *rdev,
+                                enum radeon_hpd_id hpd);
+
+static struct radeon_asic evergreen_asic = {
+        .init = &evergreen_init,
+        .fini = &evergreen_fini,
+        .suspend = &evergreen_suspend,
+        .resume = &evergreen_resume,
+        .cp_commit = NULL,
+        .gpu_reset = &evergreen_gpu_reset,
+        .vga_set_state = &r600_vga_set_state,
+        .gart_tlb_flush = &r600_pcie_gart_tlb_flush,
+        .gart_set_page = &rs600_gart_set_page,
+        .ring_test = NULL,
+        .ring_ib_execute = NULL,
+        .irq_set = NULL,
+        .irq_process = NULL,
+        .get_vblank_counter = NULL,
+        .fence_ring_emit = NULL,
+        .cs_parse = NULL,
+        .copy_blit = NULL,
+        .copy_dma = NULL,
+        .copy = NULL,
+        .get_engine_clock = &radeon_atom_get_engine_clock,
+        .set_engine_clock = &radeon_atom_set_engine_clock,
+        .get_memory_clock = &radeon_atom_get_memory_clock,
+        .set_memory_clock = &radeon_atom_set_memory_clock,
+        .set_pcie_lanes = NULL,
+        .set_clock_gating = NULL,
+        .set_surface_reg = r600_set_surface_reg,
+        .clear_surface_reg = r600_clear_surface_reg,
+        .bandwidth_update = &evergreen_bandwidth_update,
+        .hpd_init = &evergreen_hpd_init,
+        .hpd_fini = &evergreen_hpd_fini,
+        .hpd_sense = &evergreen_hpd_sense,
+        .hpd_set_polarity = &evergreen_hpd_set_polarity,
+};
+
 #endif