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path: root/drivers/gpu/drm/radeon/radeon_asic.c
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Diffstat (limited to 'drivers/gpu/drm/radeon/radeon_asic.c')
-rw-r--r--drivers/gpu/drm/radeon/radeon_asic.c24
1 files changed, 24 insertions, 0 deletions
diff --git a/drivers/gpu/drm/radeon/radeon_asic.c b/drivers/gpu/drm/radeon/radeon_asic.c
index 121aff6a3b41..ed0e10eee2dc 100644
--- a/drivers/gpu/drm/radeon/radeon_asic.c
+++ b/drivers/gpu/drm/radeon/radeon_asic.c
@@ -159,11 +159,13 @@ void radeon_agp_disable(struct radeon_device *rdev)
159 DRM_INFO("Forcing AGP to PCIE mode\n"); 159 DRM_INFO("Forcing AGP to PCIE mode\n");
160 rdev->flags |= RADEON_IS_PCIE; 160 rdev->flags |= RADEON_IS_PCIE;
161 rdev->asic->gart.tlb_flush = &rv370_pcie_gart_tlb_flush; 161 rdev->asic->gart.tlb_flush = &rv370_pcie_gart_tlb_flush;
162 rdev->asic->gart.get_page_entry = &rv370_pcie_gart_get_page_entry;
162 rdev->asic->gart.set_page = &rv370_pcie_gart_set_page; 163 rdev->asic->gart.set_page = &rv370_pcie_gart_set_page;
163 } else { 164 } else {
164 DRM_INFO("Forcing AGP to PCI mode\n"); 165 DRM_INFO("Forcing AGP to PCI mode\n");
165 rdev->flags |= RADEON_IS_PCI; 166 rdev->flags |= RADEON_IS_PCI;
166 rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush; 167 rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush;
168 rdev->asic->gart.get_page_entry = &r100_pci_gart_get_page_entry;
167 rdev->asic->gart.set_page = &r100_pci_gart_set_page; 169 rdev->asic->gart.set_page = &r100_pci_gart_set_page;
168 } 170 }
169 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024; 171 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
@@ -199,6 +201,7 @@ static struct radeon_asic r100_asic = {
199 .mc_wait_for_idle = &r100_mc_wait_for_idle, 201 .mc_wait_for_idle = &r100_mc_wait_for_idle,
200 .gart = { 202 .gart = {
201 .tlb_flush = &r100_pci_gart_tlb_flush, 203 .tlb_flush = &r100_pci_gart_tlb_flush,
204 .get_page_entry = &r100_pci_gart_get_page_entry,
202 .set_page = &r100_pci_gart_set_page, 205 .set_page = &r100_pci_gart_set_page,
203 }, 206 },
204 .ring = { 207 .ring = {
@@ -265,6 +268,7 @@ static struct radeon_asic r200_asic = {
265 .mc_wait_for_idle = &r100_mc_wait_for_idle, 268 .mc_wait_for_idle = &r100_mc_wait_for_idle,
266 .gart = { 269 .gart = {
267 .tlb_flush = &r100_pci_gart_tlb_flush, 270 .tlb_flush = &r100_pci_gart_tlb_flush,
271 .get_page_entry = &r100_pci_gart_get_page_entry,
268 .set_page = &r100_pci_gart_set_page, 272 .set_page = &r100_pci_gart_set_page,
269 }, 273 },
270 .ring = { 274 .ring = {
@@ -359,6 +363,7 @@ static struct radeon_asic r300_asic = {
359 .mc_wait_for_idle = &r300_mc_wait_for_idle, 363 .mc_wait_for_idle = &r300_mc_wait_for_idle,
360 .gart = { 364 .gart = {
361 .tlb_flush = &r100_pci_gart_tlb_flush, 365 .tlb_flush = &r100_pci_gart_tlb_flush,
366 .get_page_entry = &r100_pci_gart_get_page_entry,
362 .set_page = &r100_pci_gart_set_page, 367 .set_page = &r100_pci_gart_set_page,
363 }, 368 },
364 .ring = { 369 .ring = {
@@ -425,6 +430,7 @@ static struct radeon_asic r300_asic_pcie = {
425 .mc_wait_for_idle = &r300_mc_wait_for_idle, 430 .mc_wait_for_idle = &r300_mc_wait_for_idle,
426 .gart = { 431 .gart = {
427 .tlb_flush = &rv370_pcie_gart_tlb_flush, 432 .tlb_flush = &rv370_pcie_gart_tlb_flush,
433 .get_page_entry = &rv370_pcie_gart_get_page_entry,
428 .set_page = &rv370_pcie_gart_set_page, 434 .set_page = &rv370_pcie_gart_set_page,
429 }, 435 },
430 .ring = { 436 .ring = {
@@ -491,6 +497,7 @@ static struct radeon_asic r420_asic = {
491 .mc_wait_for_idle = &r300_mc_wait_for_idle, 497 .mc_wait_for_idle = &r300_mc_wait_for_idle,
492 .gart = { 498 .gart = {
493 .tlb_flush = &rv370_pcie_gart_tlb_flush, 499 .tlb_flush = &rv370_pcie_gart_tlb_flush,
500 .get_page_entry = &rv370_pcie_gart_get_page_entry,
494 .set_page = &rv370_pcie_gart_set_page, 501 .set_page = &rv370_pcie_gart_set_page,
495 }, 502 },
496 .ring = { 503 .ring = {
@@ -557,6 +564,7 @@ static struct radeon_asic rs400_asic = {
557 .mc_wait_for_idle = &rs400_mc_wait_for_idle, 564 .mc_wait_for_idle = &rs400_mc_wait_for_idle,
558 .gart = { 565 .gart = {
559 .tlb_flush = &rs400_gart_tlb_flush, 566 .tlb_flush = &rs400_gart_tlb_flush,
567 .get_page_entry = &rs400_gart_get_page_entry,
560 .set_page = &rs400_gart_set_page, 568 .set_page = &rs400_gart_set_page,
561 }, 569 },
562 .ring = { 570 .ring = {
@@ -623,6 +631,7 @@ static struct radeon_asic rs600_asic = {
623 .mc_wait_for_idle = &rs600_mc_wait_for_idle, 631 .mc_wait_for_idle = &rs600_mc_wait_for_idle,
624 .gart = { 632 .gart = {
625 .tlb_flush = &rs600_gart_tlb_flush, 633 .tlb_flush = &rs600_gart_tlb_flush,
634 .get_page_entry = &rs600_gart_get_page_entry,
626 .set_page = &rs600_gart_set_page, 635 .set_page = &rs600_gart_set_page,
627 }, 636 },
628 .ring = { 637 .ring = {
@@ -691,6 +700,7 @@ static struct radeon_asic rs690_asic = {
691 .mc_wait_for_idle = &rs690_mc_wait_for_idle, 700 .mc_wait_for_idle = &rs690_mc_wait_for_idle,
692 .gart = { 701 .gart = {
693 .tlb_flush = &rs400_gart_tlb_flush, 702 .tlb_flush = &rs400_gart_tlb_flush,
703 .get_page_entry = &rs400_gart_get_page_entry,
694 .set_page = &rs400_gart_set_page, 704 .set_page = &rs400_gart_set_page,
695 }, 705 },
696 .ring = { 706 .ring = {
@@ -759,6 +769,7 @@ static struct radeon_asic rv515_asic = {
759 .mc_wait_for_idle = &rv515_mc_wait_for_idle, 769 .mc_wait_for_idle = &rv515_mc_wait_for_idle,
760 .gart = { 770 .gart = {
761 .tlb_flush = &rv370_pcie_gart_tlb_flush, 771 .tlb_flush = &rv370_pcie_gart_tlb_flush,
772 .get_page_entry = &rv370_pcie_gart_get_page_entry,
762 .set_page = &rv370_pcie_gart_set_page, 773 .set_page = &rv370_pcie_gart_set_page,
763 }, 774 },
764 .ring = { 775 .ring = {
@@ -825,6 +836,7 @@ static struct radeon_asic r520_asic = {
825 .mc_wait_for_idle = &r520_mc_wait_for_idle, 836 .mc_wait_for_idle = &r520_mc_wait_for_idle,
826 .gart = { 837 .gart = {
827 .tlb_flush = &rv370_pcie_gart_tlb_flush, 838 .tlb_flush = &rv370_pcie_gart_tlb_flush,
839 .get_page_entry = &rv370_pcie_gart_get_page_entry,
828 .set_page = &rv370_pcie_gart_set_page, 840 .set_page = &rv370_pcie_gart_set_page,
829 }, 841 },
830 .ring = { 842 .ring = {
@@ -919,6 +931,7 @@ static struct radeon_asic r600_asic = {
919 .get_gpu_clock_counter = &r600_get_gpu_clock_counter, 931 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
920 .gart = { 932 .gart = {
921 .tlb_flush = &r600_pcie_gart_tlb_flush, 933 .tlb_flush = &r600_pcie_gart_tlb_flush,
934 .get_page_entry = &rs600_gart_get_page_entry,
922 .set_page = &rs600_gart_set_page, 935 .set_page = &rs600_gart_set_page,
923 }, 936 },
924 .ring = { 937 .ring = {
@@ -1004,6 +1017,7 @@ static struct radeon_asic rv6xx_asic = {
1004 .get_gpu_clock_counter = &r600_get_gpu_clock_counter, 1017 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1005 .gart = { 1018 .gart = {
1006 .tlb_flush = &r600_pcie_gart_tlb_flush, 1019 .tlb_flush = &r600_pcie_gart_tlb_flush,
1020 .get_page_entry = &rs600_gart_get_page_entry,
1007 .set_page = &rs600_gart_set_page, 1021 .set_page = &rs600_gart_set_page,
1008 }, 1022 },
1009 .ring = { 1023 .ring = {
@@ -1095,6 +1109,7 @@ static struct radeon_asic rs780_asic = {
1095 .get_gpu_clock_counter = &r600_get_gpu_clock_counter, 1109 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1096 .gart = { 1110 .gart = {
1097 .tlb_flush = &r600_pcie_gart_tlb_flush, 1111 .tlb_flush = &r600_pcie_gart_tlb_flush,
1112 .get_page_entry = &rs600_gart_get_page_entry,
1098 .set_page = &rs600_gart_set_page, 1113 .set_page = &rs600_gart_set_page,
1099 }, 1114 },
1100 .ring = { 1115 .ring = {
@@ -1199,6 +1214,7 @@ static struct radeon_asic rv770_asic = {
1199 .get_gpu_clock_counter = &r600_get_gpu_clock_counter, 1214 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1200 .gart = { 1215 .gart = {
1201 .tlb_flush = &r600_pcie_gart_tlb_flush, 1216 .tlb_flush = &r600_pcie_gart_tlb_flush,
1217 .get_page_entry = &rs600_gart_get_page_entry,
1202 .set_page = &rs600_gart_set_page, 1218 .set_page = &rs600_gart_set_page,
1203 }, 1219 },
1204 .ring = { 1220 .ring = {
@@ -1317,6 +1333,7 @@ static struct radeon_asic evergreen_asic = {
1317 .get_gpu_clock_counter = &r600_get_gpu_clock_counter, 1333 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1318 .gart = { 1334 .gart = {
1319 .tlb_flush = &evergreen_pcie_gart_tlb_flush, 1335 .tlb_flush = &evergreen_pcie_gart_tlb_flush,
1336 .get_page_entry = &rs600_gart_get_page_entry,
1320 .set_page = &rs600_gart_set_page, 1337 .set_page = &rs600_gart_set_page,
1321 }, 1338 },
1322 .ring = { 1339 .ring = {
@@ -1409,6 +1426,7 @@ static struct radeon_asic sumo_asic = {
1409 .get_gpu_clock_counter = &r600_get_gpu_clock_counter, 1426 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1410 .gart = { 1427 .gart = {
1411 .tlb_flush = &evergreen_pcie_gart_tlb_flush, 1428 .tlb_flush = &evergreen_pcie_gart_tlb_flush,
1429 .get_page_entry = &rs600_gart_get_page_entry,
1412 .set_page = &rs600_gart_set_page, 1430 .set_page = &rs600_gart_set_page,
1413 }, 1431 },
1414 .ring = { 1432 .ring = {
@@ -1500,6 +1518,7 @@ static struct radeon_asic btc_asic = {
1500 .get_gpu_clock_counter = &r600_get_gpu_clock_counter, 1518 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1501 .gart = { 1519 .gart = {
1502 .tlb_flush = &evergreen_pcie_gart_tlb_flush, 1520 .tlb_flush = &evergreen_pcie_gart_tlb_flush,
1521 .get_page_entry = &rs600_gart_get_page_entry,
1503 .set_page = &rs600_gart_set_page, 1522 .set_page = &rs600_gart_set_page,
1504 }, 1523 },
1505 .ring = { 1524 .ring = {
@@ -1635,6 +1654,7 @@ static struct radeon_asic cayman_asic = {
1635 .get_gpu_clock_counter = &r600_get_gpu_clock_counter, 1654 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1636 .gart = { 1655 .gart = {
1637 .tlb_flush = &cayman_pcie_gart_tlb_flush, 1656 .tlb_flush = &cayman_pcie_gart_tlb_flush,
1657 .get_page_entry = &rs600_gart_get_page_entry,
1638 .set_page = &rs600_gart_set_page, 1658 .set_page = &rs600_gart_set_page,
1639 }, 1659 },
1640 .vm = { 1660 .vm = {
@@ -1738,6 +1758,7 @@ static struct radeon_asic trinity_asic = {
1738 .get_gpu_clock_counter = &r600_get_gpu_clock_counter, 1758 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1739 .gart = { 1759 .gart = {
1740 .tlb_flush = &cayman_pcie_gart_tlb_flush, 1760 .tlb_flush = &cayman_pcie_gart_tlb_flush,
1761 .get_page_entry = &rs600_gart_get_page_entry,
1741 .set_page = &rs600_gart_set_page, 1762 .set_page = &rs600_gart_set_page,
1742 }, 1763 },
1743 .vm = { 1764 .vm = {
@@ -1871,6 +1892,7 @@ static struct radeon_asic si_asic = {
1871 .get_gpu_clock_counter = &si_get_gpu_clock_counter, 1892 .get_gpu_clock_counter = &si_get_gpu_clock_counter,
1872 .gart = { 1893 .gart = {
1873 .tlb_flush = &si_pcie_gart_tlb_flush, 1894 .tlb_flush = &si_pcie_gart_tlb_flush,
1895 .get_page_entry = &rs600_gart_get_page_entry,
1874 .set_page = &rs600_gart_set_page, 1896 .set_page = &rs600_gart_set_page,
1875 }, 1897 },
1876 .vm = { 1898 .vm = {
@@ -2032,6 +2054,7 @@ static struct radeon_asic ci_asic = {
2032 .get_gpu_clock_counter = &cik_get_gpu_clock_counter, 2054 .get_gpu_clock_counter = &cik_get_gpu_clock_counter,
2033 .gart = { 2055 .gart = {
2034 .tlb_flush = &cik_pcie_gart_tlb_flush, 2056 .tlb_flush = &cik_pcie_gart_tlb_flush,
2057 .get_page_entry = &rs600_gart_get_page_entry,
2035 .set_page = &rs600_gart_set_page, 2058 .set_page = &rs600_gart_set_page,
2036 }, 2059 },
2037 .vm = { 2060 .vm = {
@@ -2139,6 +2162,7 @@ static struct radeon_asic kv_asic = {
2139 .get_gpu_clock_counter = &cik_get_gpu_clock_counter, 2162 .get_gpu_clock_counter = &cik_get_gpu_clock_counter,
2140 .gart = { 2163 .gart = {
2141 .tlb_flush = &cik_pcie_gart_tlb_flush, 2164 .tlb_flush = &cik_pcie_gart_tlb_flush,
2165 .get_page_entry = &rs600_gart_get_page_entry,
2142 .set_page = &rs600_gart_set_page, 2166 .set_page = &rs600_gart_set_page,
2143 }, 2167 },
2144 .vm = { 2168 .vm = {