diff options
Diffstat (limited to 'drivers/gpu/drm/radeon/radeon_asic.c')
-rw-r--r-- | drivers/gpu/drm/radeon/radeon_asic.c | 102 |
1 files changed, 51 insertions, 51 deletions
diff --git a/drivers/gpu/drm/radeon/radeon_asic.c b/drivers/gpu/drm/radeon/radeon_asic.c index 0a59f4810187..479c89e0af17 100644 --- a/drivers/gpu/drm/radeon/radeon_asic.c +++ b/drivers/gpu/drm/radeon/radeon_asic.c | |||
@@ -136,6 +136,9 @@ static struct radeon_asic r100_asic = { | |||
136 | .vga_set_state = &r100_vga_set_state, | 136 | .vga_set_state = &r100_vga_set_state, |
137 | .gpu_is_lockup = &r100_gpu_is_lockup, | 137 | .gpu_is_lockup = &r100_gpu_is_lockup, |
138 | .asic_reset = &r100_asic_reset, | 138 | .asic_reset = &r100_asic_reset, |
139 | .ioctl_wait_idle = NULL, | ||
140 | .gui_idle = &r100_gui_idle, | ||
141 | .mc_wait_for_idle = &r100_mc_wait_for_idle, | ||
139 | .gart = { | 142 | .gart = { |
140 | .tlb_flush = &r100_pci_gart_tlb_flush, | 143 | .tlb_flush = &r100_pci_gart_tlb_flush, |
141 | .set_page = &r100_pci_gart_set_page, | 144 | .set_page = &r100_pci_gart_set_page, |
@@ -178,8 +181,6 @@ static struct radeon_asic r100_asic = { | |||
178 | .sense = &r100_hpd_sense, | 181 | .sense = &r100_hpd_sense, |
179 | .set_polarity = &r100_hpd_set_polarity, | 182 | .set_polarity = &r100_hpd_set_polarity, |
180 | }, | 183 | }, |
181 | .ioctl_wait_idle = NULL, | ||
182 | .gui_idle = &r100_gui_idle, | ||
183 | .pm = { | 184 | .pm = { |
184 | .misc = &r100_pm_misc, | 185 | .misc = &r100_pm_misc, |
185 | .prepare = &r100_pm_prepare, | 186 | .prepare = &r100_pm_prepare, |
@@ -199,7 +200,6 @@ static struct radeon_asic r100_asic = { | |||
199 | .page_flip = &r100_page_flip, | 200 | .page_flip = &r100_page_flip, |
200 | .post_page_flip = &r100_post_page_flip, | 201 | .post_page_flip = &r100_post_page_flip, |
201 | }, | 202 | }, |
202 | .mc_wait_for_idle = &r100_mc_wait_for_idle, | ||
203 | }; | 203 | }; |
204 | 204 | ||
205 | static struct radeon_asic r200_asic = { | 205 | static struct radeon_asic r200_asic = { |
@@ -210,6 +210,9 @@ static struct radeon_asic r200_asic = { | |||
210 | .vga_set_state = &r100_vga_set_state, | 210 | .vga_set_state = &r100_vga_set_state, |
211 | .gpu_is_lockup = &r100_gpu_is_lockup, | 211 | .gpu_is_lockup = &r100_gpu_is_lockup, |
212 | .asic_reset = &r100_asic_reset, | 212 | .asic_reset = &r100_asic_reset, |
213 | .ioctl_wait_idle = NULL, | ||
214 | .gui_idle = &r100_gui_idle, | ||
215 | .mc_wait_for_idle = &r100_mc_wait_for_idle, | ||
213 | .gart = { | 216 | .gart = { |
214 | .tlb_flush = &r100_pci_gart_tlb_flush, | 217 | .tlb_flush = &r100_pci_gart_tlb_flush, |
215 | .set_page = &r100_pci_gart_set_page, | 218 | .set_page = &r100_pci_gart_set_page, |
@@ -252,8 +255,6 @@ static struct radeon_asic r200_asic = { | |||
252 | .sense = &r100_hpd_sense, | 255 | .sense = &r100_hpd_sense, |
253 | .set_polarity = &r100_hpd_set_polarity, | 256 | .set_polarity = &r100_hpd_set_polarity, |
254 | }, | 257 | }, |
255 | .ioctl_wait_idle = NULL, | ||
256 | .gui_idle = &r100_gui_idle, | ||
257 | .pm = { | 258 | .pm = { |
258 | .misc = &r100_pm_misc, | 259 | .misc = &r100_pm_misc, |
259 | .prepare = &r100_pm_prepare, | 260 | .prepare = &r100_pm_prepare, |
@@ -273,7 +274,6 @@ static struct radeon_asic r200_asic = { | |||
273 | .page_flip = &r100_page_flip, | 274 | .page_flip = &r100_page_flip, |
274 | .post_page_flip = &r100_post_page_flip, | 275 | .post_page_flip = &r100_post_page_flip, |
275 | }, | 276 | }, |
276 | .mc_wait_for_idle = &r100_mc_wait_for_idle, | ||
277 | }; | 277 | }; |
278 | 278 | ||
279 | static struct radeon_asic r300_asic = { | 279 | static struct radeon_asic r300_asic = { |
@@ -284,6 +284,9 @@ static struct radeon_asic r300_asic = { | |||
284 | .vga_set_state = &r100_vga_set_state, | 284 | .vga_set_state = &r100_vga_set_state, |
285 | .gpu_is_lockup = &r300_gpu_is_lockup, | 285 | .gpu_is_lockup = &r300_gpu_is_lockup, |
286 | .asic_reset = &r300_asic_reset, | 286 | .asic_reset = &r300_asic_reset, |
287 | .ioctl_wait_idle = NULL, | ||
288 | .gui_idle = &r100_gui_idle, | ||
289 | .mc_wait_for_idle = &r300_mc_wait_for_idle, | ||
287 | .gart = { | 290 | .gart = { |
288 | .tlb_flush = &r100_pci_gart_tlb_flush, | 291 | .tlb_flush = &r100_pci_gart_tlb_flush, |
289 | .set_page = &r100_pci_gart_set_page, | 292 | .set_page = &r100_pci_gart_set_page, |
@@ -326,8 +329,6 @@ static struct radeon_asic r300_asic = { | |||
326 | .sense = &r100_hpd_sense, | 329 | .sense = &r100_hpd_sense, |
327 | .set_polarity = &r100_hpd_set_polarity, | 330 | .set_polarity = &r100_hpd_set_polarity, |
328 | }, | 331 | }, |
329 | .ioctl_wait_idle = NULL, | ||
330 | .gui_idle = &r100_gui_idle, | ||
331 | .pm = { | 332 | .pm = { |
332 | .misc = &r100_pm_misc, | 333 | .misc = &r100_pm_misc, |
333 | .prepare = &r100_pm_prepare, | 334 | .prepare = &r100_pm_prepare, |
@@ -347,7 +348,6 @@ static struct radeon_asic r300_asic = { | |||
347 | .page_flip = &r100_page_flip, | 348 | .page_flip = &r100_page_flip, |
348 | .post_page_flip = &r100_post_page_flip, | 349 | .post_page_flip = &r100_post_page_flip, |
349 | }, | 350 | }, |
350 | .mc_wait_for_idle = &r300_mc_wait_for_idle, | ||
351 | }; | 351 | }; |
352 | 352 | ||
353 | static struct radeon_asic r300_asic_pcie = { | 353 | static struct radeon_asic r300_asic_pcie = { |
@@ -358,6 +358,9 @@ static struct radeon_asic r300_asic_pcie = { | |||
358 | .vga_set_state = &r100_vga_set_state, | 358 | .vga_set_state = &r100_vga_set_state, |
359 | .gpu_is_lockup = &r300_gpu_is_lockup, | 359 | .gpu_is_lockup = &r300_gpu_is_lockup, |
360 | .asic_reset = &r300_asic_reset, | 360 | .asic_reset = &r300_asic_reset, |
361 | .ioctl_wait_idle = NULL, | ||
362 | .gui_idle = &r100_gui_idle, | ||
363 | .mc_wait_for_idle = &r300_mc_wait_for_idle, | ||
361 | .gart = { | 364 | .gart = { |
362 | .tlb_flush = &rv370_pcie_gart_tlb_flush, | 365 | .tlb_flush = &rv370_pcie_gart_tlb_flush, |
363 | .set_page = &rv370_pcie_gart_set_page, | 366 | .set_page = &rv370_pcie_gart_set_page, |
@@ -400,8 +403,6 @@ static struct radeon_asic r300_asic_pcie = { | |||
400 | .sense = &r100_hpd_sense, | 403 | .sense = &r100_hpd_sense, |
401 | .set_polarity = &r100_hpd_set_polarity, | 404 | .set_polarity = &r100_hpd_set_polarity, |
402 | }, | 405 | }, |
403 | .ioctl_wait_idle = NULL, | ||
404 | .gui_idle = &r100_gui_idle, | ||
405 | .pm = { | 406 | .pm = { |
406 | .misc = &r100_pm_misc, | 407 | .misc = &r100_pm_misc, |
407 | .prepare = &r100_pm_prepare, | 408 | .prepare = &r100_pm_prepare, |
@@ -421,7 +422,6 @@ static struct radeon_asic r300_asic_pcie = { | |||
421 | .page_flip = &r100_page_flip, | 422 | .page_flip = &r100_page_flip, |
422 | .post_page_flip = &r100_post_page_flip, | 423 | .post_page_flip = &r100_post_page_flip, |
423 | }, | 424 | }, |
424 | .mc_wait_for_idle = &r300_mc_wait_for_idle, | ||
425 | }; | 425 | }; |
426 | 426 | ||
427 | static struct radeon_asic r420_asic = { | 427 | static struct radeon_asic r420_asic = { |
@@ -432,6 +432,9 @@ static struct radeon_asic r420_asic = { | |||
432 | .vga_set_state = &r100_vga_set_state, | 432 | .vga_set_state = &r100_vga_set_state, |
433 | .gpu_is_lockup = &r300_gpu_is_lockup, | 433 | .gpu_is_lockup = &r300_gpu_is_lockup, |
434 | .asic_reset = &r300_asic_reset, | 434 | .asic_reset = &r300_asic_reset, |
435 | .ioctl_wait_idle = NULL, | ||
436 | .gui_idle = &r100_gui_idle, | ||
437 | .mc_wait_for_idle = &r300_mc_wait_for_idle, | ||
435 | .gart = { | 438 | .gart = { |
436 | .tlb_flush = &rv370_pcie_gart_tlb_flush, | 439 | .tlb_flush = &rv370_pcie_gart_tlb_flush, |
437 | .set_page = &rv370_pcie_gart_set_page, | 440 | .set_page = &rv370_pcie_gart_set_page, |
@@ -474,8 +477,6 @@ static struct radeon_asic r420_asic = { | |||
474 | .sense = &r100_hpd_sense, | 477 | .sense = &r100_hpd_sense, |
475 | .set_polarity = &r100_hpd_set_polarity, | 478 | .set_polarity = &r100_hpd_set_polarity, |
476 | }, | 479 | }, |
477 | .ioctl_wait_idle = NULL, | ||
478 | .gui_idle = &r100_gui_idle, | ||
479 | .pm = { | 480 | .pm = { |
480 | .misc = &r100_pm_misc, | 481 | .misc = &r100_pm_misc, |
481 | .prepare = &r100_pm_prepare, | 482 | .prepare = &r100_pm_prepare, |
@@ -495,7 +496,6 @@ static struct radeon_asic r420_asic = { | |||
495 | .page_flip = &r100_page_flip, | 496 | .page_flip = &r100_page_flip, |
496 | .post_page_flip = &r100_post_page_flip, | 497 | .post_page_flip = &r100_post_page_flip, |
497 | }, | 498 | }, |
498 | .mc_wait_for_idle = &r300_mc_wait_for_idle, | ||
499 | }; | 499 | }; |
500 | 500 | ||
501 | static struct radeon_asic rs400_asic = { | 501 | static struct radeon_asic rs400_asic = { |
@@ -506,6 +506,9 @@ static struct radeon_asic rs400_asic = { | |||
506 | .vga_set_state = &r100_vga_set_state, | 506 | .vga_set_state = &r100_vga_set_state, |
507 | .gpu_is_lockup = &r300_gpu_is_lockup, | 507 | .gpu_is_lockup = &r300_gpu_is_lockup, |
508 | .asic_reset = &r300_asic_reset, | 508 | .asic_reset = &r300_asic_reset, |
509 | .ioctl_wait_idle = NULL, | ||
510 | .gui_idle = &r100_gui_idle, | ||
511 | .mc_wait_for_idle = &rs400_mc_wait_for_idle, | ||
509 | .gart = { | 512 | .gart = { |
510 | .tlb_flush = &rs400_gart_tlb_flush, | 513 | .tlb_flush = &rs400_gart_tlb_flush, |
511 | .set_page = &rs400_gart_set_page, | 514 | .set_page = &rs400_gart_set_page, |
@@ -548,8 +551,6 @@ static struct radeon_asic rs400_asic = { | |||
548 | .sense = &r100_hpd_sense, | 551 | .sense = &r100_hpd_sense, |
549 | .set_polarity = &r100_hpd_set_polarity, | 552 | .set_polarity = &r100_hpd_set_polarity, |
550 | }, | 553 | }, |
551 | .ioctl_wait_idle = NULL, | ||
552 | .gui_idle = &r100_gui_idle, | ||
553 | .pm = { | 554 | .pm = { |
554 | .misc = &r100_pm_misc, | 555 | .misc = &r100_pm_misc, |
555 | .prepare = &r100_pm_prepare, | 556 | .prepare = &r100_pm_prepare, |
@@ -569,7 +570,6 @@ static struct radeon_asic rs400_asic = { | |||
569 | .page_flip = &r100_page_flip, | 570 | .page_flip = &r100_page_flip, |
570 | .post_page_flip = &r100_post_page_flip, | 571 | .post_page_flip = &r100_post_page_flip, |
571 | }, | 572 | }, |
572 | .mc_wait_for_idle = &rs400_mc_wait_for_idle, | ||
573 | }; | 573 | }; |
574 | 574 | ||
575 | static struct radeon_asic rs600_asic = { | 575 | static struct radeon_asic rs600_asic = { |
@@ -580,6 +580,9 @@ static struct radeon_asic rs600_asic = { | |||
580 | .vga_set_state = &r100_vga_set_state, | 580 | .vga_set_state = &r100_vga_set_state, |
581 | .gpu_is_lockup = &r300_gpu_is_lockup, | 581 | .gpu_is_lockup = &r300_gpu_is_lockup, |
582 | .asic_reset = &rs600_asic_reset, | 582 | .asic_reset = &rs600_asic_reset, |
583 | .ioctl_wait_idle = NULL, | ||
584 | .gui_idle = &r100_gui_idle, | ||
585 | .mc_wait_for_idle = &rs600_mc_wait_for_idle, | ||
583 | .gart = { | 586 | .gart = { |
584 | .tlb_flush = &rs600_gart_tlb_flush, | 587 | .tlb_flush = &rs600_gart_tlb_flush, |
585 | .set_page = &rs600_gart_set_page, | 588 | .set_page = &rs600_gart_set_page, |
@@ -622,8 +625,6 @@ static struct radeon_asic rs600_asic = { | |||
622 | .sense = &rs600_hpd_sense, | 625 | .sense = &rs600_hpd_sense, |
623 | .set_polarity = &rs600_hpd_set_polarity, | 626 | .set_polarity = &rs600_hpd_set_polarity, |
624 | }, | 627 | }, |
625 | .ioctl_wait_idle = NULL, | ||
626 | .gui_idle = &r100_gui_idle, | ||
627 | .pm = { | 628 | .pm = { |
628 | .misc = &rs600_pm_misc, | 629 | .misc = &rs600_pm_misc, |
629 | .prepare = &rs600_pm_prepare, | 630 | .prepare = &rs600_pm_prepare, |
@@ -643,7 +644,6 @@ static struct radeon_asic rs600_asic = { | |||
643 | .page_flip = &rs600_page_flip, | 644 | .page_flip = &rs600_page_flip, |
644 | .post_page_flip = &rs600_post_page_flip, | 645 | .post_page_flip = &rs600_post_page_flip, |
645 | }, | 646 | }, |
646 | .mc_wait_for_idle = &rs600_mc_wait_for_idle, | ||
647 | }; | 647 | }; |
648 | 648 | ||
649 | static struct radeon_asic rs690_asic = { | 649 | static struct radeon_asic rs690_asic = { |
@@ -654,6 +654,9 @@ static struct radeon_asic rs690_asic = { | |||
654 | .vga_set_state = &r100_vga_set_state, | 654 | .vga_set_state = &r100_vga_set_state, |
655 | .gpu_is_lockup = &r300_gpu_is_lockup, | 655 | .gpu_is_lockup = &r300_gpu_is_lockup, |
656 | .asic_reset = &rs600_asic_reset, | 656 | .asic_reset = &rs600_asic_reset, |
657 | .ioctl_wait_idle = NULL, | ||
658 | .gui_idle = &r100_gui_idle, | ||
659 | .mc_wait_for_idle = &rs690_mc_wait_for_idle, | ||
657 | .gart = { | 660 | .gart = { |
658 | .tlb_flush = &rs400_gart_tlb_flush, | 661 | .tlb_flush = &rs400_gart_tlb_flush, |
659 | .set_page = &rs400_gart_set_page, | 662 | .set_page = &rs400_gart_set_page, |
@@ -696,8 +699,6 @@ static struct radeon_asic rs690_asic = { | |||
696 | .sense = &rs600_hpd_sense, | 699 | .sense = &rs600_hpd_sense, |
697 | .set_polarity = &rs600_hpd_set_polarity, | 700 | .set_polarity = &rs600_hpd_set_polarity, |
698 | }, | 701 | }, |
699 | .ioctl_wait_idle = NULL, | ||
700 | .gui_idle = &r100_gui_idle, | ||
701 | .pm = { | 702 | .pm = { |
702 | .misc = &rs600_pm_misc, | 703 | .misc = &rs600_pm_misc, |
703 | .prepare = &rs600_pm_prepare, | 704 | .prepare = &rs600_pm_prepare, |
@@ -717,7 +718,6 @@ static struct radeon_asic rs690_asic = { | |||
717 | .page_flip = &rs600_page_flip, | 718 | .page_flip = &rs600_page_flip, |
718 | .post_page_flip = &rs600_post_page_flip, | 719 | .post_page_flip = &rs600_post_page_flip, |
719 | }, | 720 | }, |
720 | .mc_wait_for_idle = &rs690_mc_wait_for_idle, | ||
721 | }; | 721 | }; |
722 | 722 | ||
723 | static struct radeon_asic rv515_asic = { | 723 | static struct radeon_asic rv515_asic = { |
@@ -728,6 +728,9 @@ static struct radeon_asic rv515_asic = { | |||
728 | .vga_set_state = &r100_vga_set_state, | 728 | .vga_set_state = &r100_vga_set_state, |
729 | .gpu_is_lockup = &r300_gpu_is_lockup, | 729 | .gpu_is_lockup = &r300_gpu_is_lockup, |
730 | .asic_reset = &rs600_asic_reset, | 730 | .asic_reset = &rs600_asic_reset, |
731 | .ioctl_wait_idle = NULL, | ||
732 | .gui_idle = &r100_gui_idle, | ||
733 | .mc_wait_for_idle = &rv515_mc_wait_for_idle, | ||
731 | .gart = { | 734 | .gart = { |
732 | .tlb_flush = &rv370_pcie_gart_tlb_flush, | 735 | .tlb_flush = &rv370_pcie_gart_tlb_flush, |
733 | .set_page = &rv370_pcie_gart_set_page, | 736 | .set_page = &rv370_pcie_gart_set_page, |
@@ -770,8 +773,6 @@ static struct radeon_asic rv515_asic = { | |||
770 | .sense = &rs600_hpd_sense, | 773 | .sense = &rs600_hpd_sense, |
771 | .set_polarity = &rs600_hpd_set_polarity, | 774 | .set_polarity = &rs600_hpd_set_polarity, |
772 | }, | 775 | }, |
773 | .ioctl_wait_idle = NULL, | ||
774 | .gui_idle = &r100_gui_idle, | ||
775 | .pm = { | 776 | .pm = { |
776 | .misc = &rs600_pm_misc, | 777 | .misc = &rs600_pm_misc, |
777 | .prepare = &rs600_pm_prepare, | 778 | .prepare = &rs600_pm_prepare, |
@@ -791,7 +792,6 @@ static struct radeon_asic rv515_asic = { | |||
791 | .page_flip = &rs600_page_flip, | 792 | .page_flip = &rs600_page_flip, |
792 | .post_page_flip = &rs600_post_page_flip, | 793 | .post_page_flip = &rs600_post_page_flip, |
793 | }, | 794 | }, |
794 | .mc_wait_for_idle = &rv515_mc_wait_for_idle, | ||
795 | }; | 795 | }; |
796 | 796 | ||
797 | static struct radeon_asic r520_asic = { | 797 | static struct radeon_asic r520_asic = { |
@@ -802,6 +802,9 @@ static struct radeon_asic r520_asic = { | |||
802 | .vga_set_state = &r100_vga_set_state, | 802 | .vga_set_state = &r100_vga_set_state, |
803 | .gpu_is_lockup = &r300_gpu_is_lockup, | 803 | .gpu_is_lockup = &r300_gpu_is_lockup, |
804 | .asic_reset = &rs600_asic_reset, | 804 | .asic_reset = &rs600_asic_reset, |
805 | .ioctl_wait_idle = NULL, | ||
806 | .gui_idle = &r100_gui_idle, | ||
807 | .mc_wait_for_idle = &r520_mc_wait_for_idle, | ||
805 | .gart = { | 808 | .gart = { |
806 | .tlb_flush = &rv370_pcie_gart_tlb_flush, | 809 | .tlb_flush = &rv370_pcie_gart_tlb_flush, |
807 | .set_page = &rv370_pcie_gart_set_page, | 810 | .set_page = &rv370_pcie_gart_set_page, |
@@ -844,8 +847,6 @@ static struct radeon_asic r520_asic = { | |||
844 | .sense = &rs600_hpd_sense, | 847 | .sense = &rs600_hpd_sense, |
845 | .set_polarity = &rs600_hpd_set_polarity, | 848 | .set_polarity = &rs600_hpd_set_polarity, |
846 | }, | 849 | }, |
847 | .ioctl_wait_idle = NULL, | ||
848 | .gui_idle = &r100_gui_idle, | ||
849 | .pm = { | 850 | .pm = { |
850 | .misc = &rs600_pm_misc, | 851 | .misc = &rs600_pm_misc, |
851 | .prepare = &rs600_pm_prepare, | 852 | .prepare = &rs600_pm_prepare, |
@@ -865,7 +866,6 @@ static struct radeon_asic r520_asic = { | |||
865 | .page_flip = &rs600_page_flip, | 866 | .page_flip = &rs600_page_flip, |
866 | .post_page_flip = &rs600_post_page_flip, | 867 | .post_page_flip = &rs600_post_page_flip, |
867 | }, | 868 | }, |
868 | .mc_wait_for_idle = &r520_mc_wait_for_idle, | ||
869 | }; | 869 | }; |
870 | 870 | ||
871 | static struct radeon_asic r600_asic = { | 871 | static struct radeon_asic r600_asic = { |
@@ -876,6 +876,9 @@ static struct radeon_asic r600_asic = { | |||
876 | .vga_set_state = &r600_vga_set_state, | 876 | .vga_set_state = &r600_vga_set_state, |
877 | .gpu_is_lockup = &r600_gpu_is_lockup, | 877 | .gpu_is_lockup = &r600_gpu_is_lockup, |
878 | .asic_reset = &r600_asic_reset, | 878 | .asic_reset = &r600_asic_reset, |
879 | .ioctl_wait_idle = r600_ioctl_wait_idle, | ||
880 | .gui_idle = &r600_gui_idle, | ||
881 | .mc_wait_for_idle = &r600_mc_wait_for_idle, | ||
879 | .gart = { | 882 | .gart = { |
880 | .tlb_flush = &r600_pcie_gart_tlb_flush, | 883 | .tlb_flush = &r600_pcie_gart_tlb_flush, |
881 | .set_page = &rs600_gart_set_page, | 884 | .set_page = &rs600_gart_set_page, |
@@ -917,8 +920,6 @@ static struct radeon_asic r600_asic = { | |||
917 | .sense = &r600_hpd_sense, | 920 | .sense = &r600_hpd_sense, |
918 | .set_polarity = &r600_hpd_set_polarity, | 921 | .set_polarity = &r600_hpd_set_polarity, |
919 | }, | 922 | }, |
920 | .ioctl_wait_idle = r600_ioctl_wait_idle, | ||
921 | .gui_idle = &r600_gui_idle, | ||
922 | .pm = { | 923 | .pm = { |
923 | .misc = &r600_pm_misc, | 924 | .misc = &r600_pm_misc, |
924 | .prepare = &rs600_pm_prepare, | 925 | .prepare = &rs600_pm_prepare, |
@@ -938,7 +939,6 @@ static struct radeon_asic r600_asic = { | |||
938 | .page_flip = &rs600_page_flip, | 939 | .page_flip = &rs600_page_flip, |
939 | .post_page_flip = &rs600_post_page_flip, | 940 | .post_page_flip = &rs600_post_page_flip, |
940 | }, | 941 | }, |
941 | .mc_wait_for_idle = &r600_mc_wait_for_idle, | ||
942 | }; | 942 | }; |
943 | 943 | ||
944 | static struct radeon_asic rs780_asic = { | 944 | static struct radeon_asic rs780_asic = { |
@@ -949,6 +949,9 @@ static struct radeon_asic rs780_asic = { | |||
949 | .gpu_is_lockup = &r600_gpu_is_lockup, | 949 | .gpu_is_lockup = &r600_gpu_is_lockup, |
950 | .vga_set_state = &r600_vga_set_state, | 950 | .vga_set_state = &r600_vga_set_state, |
951 | .asic_reset = &r600_asic_reset, | 951 | .asic_reset = &r600_asic_reset, |
952 | .ioctl_wait_idle = r600_ioctl_wait_idle, | ||
953 | .gui_idle = &r600_gui_idle, | ||
954 | .mc_wait_for_idle = &r600_mc_wait_for_idle, | ||
952 | .gart = { | 955 | .gart = { |
953 | .tlb_flush = &r600_pcie_gart_tlb_flush, | 956 | .tlb_flush = &r600_pcie_gart_tlb_flush, |
954 | .set_page = &rs600_gart_set_page, | 957 | .set_page = &rs600_gart_set_page, |
@@ -990,8 +993,6 @@ static struct radeon_asic rs780_asic = { | |||
990 | .sense = &r600_hpd_sense, | 993 | .sense = &r600_hpd_sense, |
991 | .set_polarity = &r600_hpd_set_polarity, | 994 | .set_polarity = &r600_hpd_set_polarity, |
992 | }, | 995 | }, |
993 | .ioctl_wait_idle = r600_ioctl_wait_idle, | ||
994 | .gui_idle = &r600_gui_idle, | ||
995 | .pm = { | 996 | .pm = { |
996 | .misc = &r600_pm_misc, | 997 | .misc = &r600_pm_misc, |
997 | .prepare = &rs600_pm_prepare, | 998 | .prepare = &rs600_pm_prepare, |
@@ -1011,7 +1012,6 @@ static struct radeon_asic rs780_asic = { | |||
1011 | .page_flip = &rs600_page_flip, | 1012 | .page_flip = &rs600_page_flip, |
1012 | .post_page_flip = &rs600_post_page_flip, | 1013 | .post_page_flip = &rs600_post_page_flip, |
1013 | }, | 1014 | }, |
1014 | .mc_wait_for_idle = &r600_mc_wait_for_idle, | ||
1015 | }; | 1015 | }; |
1016 | 1016 | ||
1017 | static struct radeon_asic rv770_asic = { | 1017 | static struct radeon_asic rv770_asic = { |
@@ -1022,6 +1022,9 @@ static struct radeon_asic rv770_asic = { | |||
1022 | .asic_reset = &r600_asic_reset, | 1022 | .asic_reset = &r600_asic_reset, |
1023 | .gpu_is_lockup = &r600_gpu_is_lockup, | 1023 | .gpu_is_lockup = &r600_gpu_is_lockup, |
1024 | .vga_set_state = &r600_vga_set_state, | 1024 | .vga_set_state = &r600_vga_set_state, |
1025 | .ioctl_wait_idle = r600_ioctl_wait_idle, | ||
1026 | .gui_idle = &r600_gui_idle, | ||
1027 | .mc_wait_for_idle = &r600_mc_wait_for_idle, | ||
1025 | .gart = { | 1028 | .gart = { |
1026 | .tlb_flush = &r600_pcie_gart_tlb_flush, | 1029 | .tlb_flush = &r600_pcie_gart_tlb_flush, |
1027 | .set_page = &rs600_gart_set_page, | 1030 | .set_page = &rs600_gart_set_page, |
@@ -1063,8 +1066,6 @@ static struct radeon_asic rv770_asic = { | |||
1063 | .sense = &r600_hpd_sense, | 1066 | .sense = &r600_hpd_sense, |
1064 | .set_polarity = &r600_hpd_set_polarity, | 1067 | .set_polarity = &r600_hpd_set_polarity, |
1065 | }, | 1068 | }, |
1066 | .ioctl_wait_idle = r600_ioctl_wait_idle, | ||
1067 | .gui_idle = &r600_gui_idle, | ||
1068 | .pm = { | 1069 | .pm = { |
1069 | .misc = &rv770_pm_misc, | 1070 | .misc = &rv770_pm_misc, |
1070 | .prepare = &rs600_pm_prepare, | 1071 | .prepare = &rs600_pm_prepare, |
@@ -1084,7 +1085,6 @@ static struct radeon_asic rv770_asic = { | |||
1084 | .page_flip = &rv770_page_flip, | 1085 | .page_flip = &rv770_page_flip, |
1085 | .post_page_flip = &rs600_post_page_flip, | 1086 | .post_page_flip = &rs600_post_page_flip, |
1086 | }, | 1087 | }, |
1087 | .mc_wait_for_idle = &r600_mc_wait_for_idle, | ||
1088 | }; | 1088 | }; |
1089 | 1089 | ||
1090 | static struct radeon_asic evergreen_asic = { | 1090 | static struct radeon_asic evergreen_asic = { |
@@ -1095,6 +1095,9 @@ static struct radeon_asic evergreen_asic = { | |||
1095 | .gpu_is_lockup = &evergreen_gpu_is_lockup, | 1095 | .gpu_is_lockup = &evergreen_gpu_is_lockup, |
1096 | .asic_reset = &evergreen_asic_reset, | 1096 | .asic_reset = &evergreen_asic_reset, |
1097 | .vga_set_state = &r600_vga_set_state, | 1097 | .vga_set_state = &r600_vga_set_state, |
1098 | .ioctl_wait_idle = r600_ioctl_wait_idle, | ||
1099 | .gui_idle = &r600_gui_idle, | ||
1100 | .mc_wait_for_idle = &evergreen_mc_wait_for_idle, | ||
1098 | .gart = { | 1101 | .gart = { |
1099 | .tlb_flush = &evergreen_pcie_gart_tlb_flush, | 1102 | .tlb_flush = &evergreen_pcie_gart_tlb_flush, |
1100 | .set_page = &rs600_gart_set_page, | 1103 | .set_page = &rs600_gart_set_page, |
@@ -1136,8 +1139,6 @@ static struct radeon_asic evergreen_asic = { | |||
1136 | .sense = &evergreen_hpd_sense, | 1139 | .sense = &evergreen_hpd_sense, |
1137 | .set_polarity = &evergreen_hpd_set_polarity, | 1140 | .set_polarity = &evergreen_hpd_set_polarity, |
1138 | }, | 1141 | }, |
1139 | .ioctl_wait_idle = r600_ioctl_wait_idle, | ||
1140 | .gui_idle = &r600_gui_idle, | ||
1141 | .pm = { | 1142 | .pm = { |
1142 | .misc = &evergreen_pm_misc, | 1143 | .misc = &evergreen_pm_misc, |
1143 | .prepare = &evergreen_pm_prepare, | 1144 | .prepare = &evergreen_pm_prepare, |
@@ -1157,7 +1158,6 @@ static struct radeon_asic evergreen_asic = { | |||
1157 | .page_flip = &evergreen_page_flip, | 1158 | .page_flip = &evergreen_page_flip, |
1158 | .post_page_flip = &evergreen_post_page_flip, | 1159 | .post_page_flip = &evergreen_post_page_flip, |
1159 | }, | 1160 | }, |
1160 | .mc_wait_for_idle = &evergreen_mc_wait_for_idle, | ||
1161 | }; | 1161 | }; |
1162 | 1162 | ||
1163 | static struct radeon_asic sumo_asic = { | 1163 | static struct radeon_asic sumo_asic = { |
@@ -1168,6 +1168,9 @@ static struct radeon_asic sumo_asic = { | |||
1168 | .gpu_is_lockup = &evergreen_gpu_is_lockup, | 1168 | .gpu_is_lockup = &evergreen_gpu_is_lockup, |
1169 | .asic_reset = &evergreen_asic_reset, | 1169 | .asic_reset = &evergreen_asic_reset, |
1170 | .vga_set_state = &r600_vga_set_state, | 1170 | .vga_set_state = &r600_vga_set_state, |
1171 | .ioctl_wait_idle = r600_ioctl_wait_idle, | ||
1172 | .gui_idle = &r600_gui_idle, | ||
1173 | .mc_wait_for_idle = &evergreen_mc_wait_for_idle, | ||
1171 | .gart = { | 1174 | .gart = { |
1172 | .tlb_flush = &evergreen_pcie_gart_tlb_flush, | 1175 | .tlb_flush = &evergreen_pcie_gart_tlb_flush, |
1173 | .set_page = &rs600_gart_set_page, | 1176 | .set_page = &rs600_gart_set_page, |
@@ -1209,8 +1212,6 @@ static struct radeon_asic sumo_asic = { | |||
1209 | .sense = &evergreen_hpd_sense, | 1212 | .sense = &evergreen_hpd_sense, |
1210 | .set_polarity = &evergreen_hpd_set_polarity, | 1213 | .set_polarity = &evergreen_hpd_set_polarity, |
1211 | }, | 1214 | }, |
1212 | .ioctl_wait_idle = r600_ioctl_wait_idle, | ||
1213 | .gui_idle = &r600_gui_idle, | ||
1214 | .pm = { | 1215 | .pm = { |
1215 | .misc = &evergreen_pm_misc, | 1216 | .misc = &evergreen_pm_misc, |
1216 | .prepare = &evergreen_pm_prepare, | 1217 | .prepare = &evergreen_pm_prepare, |
@@ -1230,7 +1231,6 @@ static struct radeon_asic sumo_asic = { | |||
1230 | .page_flip = &evergreen_page_flip, | 1231 | .page_flip = &evergreen_page_flip, |
1231 | .post_page_flip = &evergreen_post_page_flip, | 1232 | .post_page_flip = &evergreen_post_page_flip, |
1232 | }, | 1233 | }, |
1233 | .mc_wait_for_idle = &evergreen_mc_wait_for_idle, | ||
1234 | }; | 1234 | }; |
1235 | 1235 | ||
1236 | static struct radeon_asic btc_asic = { | 1236 | static struct radeon_asic btc_asic = { |
@@ -1241,6 +1241,9 @@ static struct radeon_asic btc_asic = { | |||
1241 | .gpu_is_lockup = &evergreen_gpu_is_lockup, | 1241 | .gpu_is_lockup = &evergreen_gpu_is_lockup, |
1242 | .asic_reset = &evergreen_asic_reset, | 1242 | .asic_reset = &evergreen_asic_reset, |
1243 | .vga_set_state = &r600_vga_set_state, | 1243 | .vga_set_state = &r600_vga_set_state, |
1244 | .ioctl_wait_idle = r600_ioctl_wait_idle, | ||
1245 | .gui_idle = &r600_gui_idle, | ||
1246 | .mc_wait_for_idle = &evergreen_mc_wait_for_idle, | ||
1244 | .gart = { | 1247 | .gart = { |
1245 | .tlb_flush = &evergreen_pcie_gart_tlb_flush, | 1248 | .tlb_flush = &evergreen_pcie_gart_tlb_flush, |
1246 | .set_page = &rs600_gart_set_page, | 1249 | .set_page = &rs600_gart_set_page, |
@@ -1282,8 +1285,6 @@ static struct radeon_asic btc_asic = { | |||
1282 | .sense = &evergreen_hpd_sense, | 1285 | .sense = &evergreen_hpd_sense, |
1283 | .set_polarity = &evergreen_hpd_set_polarity, | 1286 | .set_polarity = &evergreen_hpd_set_polarity, |
1284 | }, | 1287 | }, |
1285 | .ioctl_wait_idle = r600_ioctl_wait_idle, | ||
1286 | .gui_idle = &r600_gui_idle, | ||
1287 | .pm = { | 1288 | .pm = { |
1288 | .misc = &evergreen_pm_misc, | 1289 | .misc = &evergreen_pm_misc, |
1289 | .prepare = &evergreen_pm_prepare, | 1290 | .prepare = &evergreen_pm_prepare, |
@@ -1303,7 +1304,6 @@ static struct radeon_asic btc_asic = { | |||
1303 | .page_flip = &evergreen_page_flip, | 1304 | .page_flip = &evergreen_page_flip, |
1304 | .post_page_flip = &evergreen_post_page_flip, | 1305 | .post_page_flip = &evergreen_post_page_flip, |
1305 | }, | 1306 | }, |
1306 | .mc_wait_for_idle = &evergreen_mc_wait_for_idle, | ||
1307 | }; | 1307 | }; |
1308 | 1308 | ||
1309 | static const struct radeon_vm_funcs cayman_vm_funcs = { | 1309 | static const struct radeon_vm_funcs cayman_vm_funcs = { |
@@ -1324,6 +1324,9 @@ static struct radeon_asic cayman_asic = { | |||
1324 | .gpu_is_lockup = &cayman_gpu_is_lockup, | 1324 | .gpu_is_lockup = &cayman_gpu_is_lockup, |
1325 | .asic_reset = &cayman_asic_reset, | 1325 | .asic_reset = &cayman_asic_reset, |
1326 | .vga_set_state = &r600_vga_set_state, | 1326 | .vga_set_state = &r600_vga_set_state, |
1327 | .ioctl_wait_idle = r600_ioctl_wait_idle, | ||
1328 | .gui_idle = &r600_gui_idle, | ||
1329 | .mc_wait_for_idle = &evergreen_mc_wait_for_idle, | ||
1327 | .gart = { | 1330 | .gart = { |
1328 | .tlb_flush = &cayman_pcie_gart_tlb_flush, | 1331 | .tlb_flush = &cayman_pcie_gart_tlb_flush, |
1329 | .set_page = &rs600_gart_set_page, | 1332 | .set_page = &rs600_gart_set_page, |
@@ -1384,8 +1387,6 @@ static struct radeon_asic cayman_asic = { | |||
1384 | .sense = &evergreen_hpd_sense, | 1387 | .sense = &evergreen_hpd_sense, |
1385 | .set_polarity = &evergreen_hpd_set_polarity, | 1388 | .set_polarity = &evergreen_hpd_set_polarity, |
1386 | }, | 1389 | }, |
1387 | .ioctl_wait_idle = r600_ioctl_wait_idle, | ||
1388 | .gui_idle = &r600_gui_idle, | ||
1389 | .pm = { | 1390 | .pm = { |
1390 | .misc = &evergreen_pm_misc, | 1391 | .misc = &evergreen_pm_misc, |
1391 | .prepare = &evergreen_pm_prepare, | 1392 | .prepare = &evergreen_pm_prepare, |
@@ -1405,7 +1406,6 @@ static struct radeon_asic cayman_asic = { | |||
1405 | .page_flip = &evergreen_page_flip, | 1406 | .page_flip = &evergreen_page_flip, |
1406 | .post_page_flip = &evergreen_post_page_flip, | 1407 | .post_page_flip = &evergreen_post_page_flip, |
1407 | }, | 1408 | }, |
1408 | .mc_wait_for_idle = &evergreen_mc_wait_for_idle, | ||
1409 | }; | 1409 | }; |
1410 | 1410 | ||
1411 | int radeon_asic_init(struct radeon_device *rdev) | 1411 | int radeon_asic_init(struct radeon_device *rdev) |