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path: root/drivers/gpu/drm/radeon/radeon.h
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Diffstat (limited to 'drivers/gpu/drm/radeon/radeon.h')
-rw-r--r--drivers/gpu/drm/radeon/radeon.h162
1 files changed, 98 insertions, 64 deletions
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index a9717b3fbf1b..54529b837afa 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -150,9 +150,6 @@ extern int radeon_backlight;
150/* number of hw syncs before falling back on blocking */ 150/* number of hw syncs before falling back on blocking */
151#define RADEON_NUM_SYNCS 4 151#define RADEON_NUM_SYNCS 4
152 152
153/* number of hw syncs before falling back on blocking */
154#define RADEON_NUM_SYNCS 4
155
156/* hardcode those limit for now */ 153/* hardcode those limit for now */
157#define RADEON_VA_IB_OFFSET (1 << 20) 154#define RADEON_VA_IB_OFFSET (1 << 20)
158#define RADEON_VA_RESERVED_SIZE (8 << 20) 155#define RADEON_VA_RESERVED_SIZE (8 << 20)
@@ -363,14 +360,15 @@ struct radeon_fence_driver {
363}; 360};
364 361
365struct radeon_fence { 362struct radeon_fence {
366 struct fence base; 363 struct fence base;
367 364
368 struct radeon_device *rdev; 365 struct radeon_device *rdev;
369 uint64_t seq; 366 uint64_t seq;
370 /* RB, DMA, etc. */ 367 /* RB, DMA, etc. */
371 unsigned ring; 368 unsigned ring;
369 bool is_vm_update;
372 370
373 wait_queue_t fence_wake; 371 wait_queue_t fence_wake;
374}; 372};
375 373
376int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring); 374int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring);
@@ -452,12 +450,22 @@ struct radeon_mman {
452#endif 450#endif
453}; 451};
454 452
453struct radeon_bo_list {
454 struct radeon_bo *robj;
455 struct ttm_validate_buffer tv;
456 uint64_t gpu_offset;
457 unsigned prefered_domains;
458 unsigned allowed_domains;
459 uint32_t tiling_flags;
460};
461
455/* bo virtual address in a specific vm */ 462/* bo virtual address in a specific vm */
456struct radeon_bo_va { 463struct radeon_bo_va {
457 /* protected by bo being reserved */ 464 /* protected by bo being reserved */
458 struct list_head bo_list; 465 struct list_head bo_list;
459 uint32_t flags; 466 uint32_t flags;
460 uint64_t addr; 467 uint64_t addr;
468 struct radeon_fence *last_pt_update;
461 unsigned ref_count; 469 unsigned ref_count;
462 470
463 /* protected by vm mutex */ 471 /* protected by vm mutex */
@@ -474,7 +482,7 @@ struct radeon_bo {
474 struct list_head list; 482 struct list_head list;
475 /* Protected by tbo.reserved */ 483 /* Protected by tbo.reserved */
476 u32 initial_domain; 484 u32 initial_domain;
477 struct ttm_place placements[3]; 485 struct ttm_place placements[4];
478 struct ttm_placement placement; 486 struct ttm_placement placement;
479 struct ttm_buffer_object tbo; 487 struct ttm_buffer_object tbo;
480 struct ttm_bo_kmap_obj kmap; 488 struct ttm_bo_kmap_obj kmap;
@@ -576,10 +584,9 @@ int radeon_mode_dumb_mmap(struct drm_file *filp,
576 * Semaphores. 584 * Semaphores.
577 */ 585 */
578struct radeon_semaphore { 586struct radeon_semaphore {
579 struct radeon_sa_bo *sa_bo; 587 struct radeon_sa_bo *sa_bo;
580 signed waiters; 588 signed waiters;
581 uint64_t gpu_addr; 589 uint64_t gpu_addr;
582 struct radeon_fence *sync_to[RADEON_NUM_RINGS];
583}; 590};
584 591
585int radeon_semaphore_create(struct radeon_device *rdev, 592int radeon_semaphore_create(struct radeon_device *rdev,
@@ -588,20 +595,33 @@ bool radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring,
588 struct radeon_semaphore *semaphore); 595 struct radeon_semaphore *semaphore);
589bool radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring, 596bool radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring,
590 struct radeon_semaphore *semaphore); 597 struct radeon_semaphore *semaphore);
591void radeon_semaphore_sync_fence(struct radeon_semaphore *semaphore,
592 struct radeon_fence *fence);
593int radeon_semaphore_sync_resv(struct radeon_device *rdev,
594 struct radeon_semaphore *semaphore,
595 struct reservation_object *resv,
596 bool shared);
597int radeon_semaphore_sync_rings(struct radeon_device *rdev,
598 struct radeon_semaphore *semaphore,
599 int waiting_ring);
600void radeon_semaphore_free(struct radeon_device *rdev, 598void radeon_semaphore_free(struct radeon_device *rdev,
601 struct radeon_semaphore **semaphore, 599 struct radeon_semaphore **semaphore,
602 struct radeon_fence *fence); 600 struct radeon_fence *fence);
603 601
604/* 602/*
603 * Synchronization
604 */
605struct radeon_sync {
606 struct radeon_semaphore *semaphores[RADEON_NUM_SYNCS];
607 struct radeon_fence *sync_to[RADEON_NUM_RINGS];
608 struct radeon_fence *last_vm_update;
609};
610
611void radeon_sync_create(struct radeon_sync *sync);
612void radeon_sync_fence(struct radeon_sync *sync,
613 struct radeon_fence *fence);
614int radeon_sync_resv(struct radeon_device *rdev,
615 struct radeon_sync *sync,
616 struct reservation_object *resv,
617 bool shared);
618int radeon_sync_rings(struct radeon_device *rdev,
619 struct radeon_sync *sync,
620 int waiting_ring);
621void radeon_sync_free(struct radeon_device *rdev, struct radeon_sync *sync,
622 struct radeon_fence *fence);
623
624/*
605 * GART structures, functions & helpers 625 * GART structures, functions & helpers
606 */ 626 */
607struct radeon_mc; 627struct radeon_mc;
@@ -701,6 +721,10 @@ struct radeon_doorbell {
701 721
702int radeon_doorbell_get(struct radeon_device *rdev, u32 *page); 722int radeon_doorbell_get(struct radeon_device *rdev, u32 *page);
703void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell); 723void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell);
724void radeon_doorbell_get_kfd_info(struct radeon_device *rdev,
725 phys_addr_t *aperture_base,
726 size_t *aperture_size,
727 size_t *start_offset);
704 728
705/* 729/*
706 * IRQS. 730 * IRQS.
@@ -814,7 +838,7 @@ struct radeon_ib {
814 struct radeon_fence *fence; 838 struct radeon_fence *fence;
815 struct radeon_vm *vm; 839 struct radeon_vm *vm;
816 bool is_const_ib; 840 bool is_const_ib;
817 struct radeon_semaphore *semaphore; 841 struct radeon_sync sync;
818}; 842};
819 843
820struct radeon_ring { 844struct radeon_ring {
@@ -891,33 +915,40 @@ struct radeon_vm_pt {
891 uint64_t addr; 915 uint64_t addr;
892}; 916};
893 917
918struct radeon_vm_id {
919 unsigned id;
920 uint64_t pd_gpu_addr;
921 /* last flushed PD/PT update */
922 struct radeon_fence *flushed_updates;
923 /* last use of vmid */
924 struct radeon_fence *last_id_use;
925};
926
894struct radeon_vm { 927struct radeon_vm {
895 struct rb_root va; 928 struct mutex mutex;
896 unsigned id; 929
930 struct rb_root va;
931
932 /* protecting invalidated and freed */
933 spinlock_t status_lock;
897 934
898 /* BOs moved, but not yet updated in the PT */ 935 /* BOs moved, but not yet updated in the PT */
899 struct list_head invalidated; 936 struct list_head invalidated;
900 937
901 /* BOs freed, but not yet updated in the PT */ 938 /* BOs freed, but not yet updated in the PT */
902 struct list_head freed; 939 struct list_head freed;
903 940
904 /* contains the page directory */ 941 /* contains the page directory */
905 struct radeon_bo *page_directory; 942 struct radeon_bo *page_directory;
906 uint64_t pd_gpu_addr; 943 unsigned max_pde_used;
907 unsigned max_pde_used;
908 944
909 /* array of page tables, one for each page directory entry */ 945 /* array of page tables, one for each page directory entry */
910 struct radeon_vm_pt *page_tables; 946 struct radeon_vm_pt *page_tables;
911 947
912 struct radeon_bo_va *ib_bo_va; 948 struct radeon_bo_va *ib_bo_va;
913 949
914 struct mutex mutex; 950 /* for id and flush management per ring */
915 /* last fence for cs using this vm */ 951 struct radeon_vm_id ids[RADEON_NUM_RINGS];
916 struct radeon_fence *fence;
917 /* last flush or NULL if we still need to flush */
918 struct radeon_fence *last_flush;
919 /* last use of vmid */
920 struct radeon_fence *last_id_use;
921}; 952};
922 953
923struct radeon_vm_manager { 954struct radeon_vm_manager {
@@ -1025,19 +1056,7 @@ void cayman_dma_fini(struct radeon_device *rdev);
1025/* 1056/*
1026 * CS. 1057 * CS.
1027 */ 1058 */
1028struct radeon_cs_reloc {
1029 struct drm_gem_object *gobj;
1030 struct radeon_bo *robj;
1031 struct ttm_validate_buffer tv;
1032 uint64_t gpu_offset;
1033 unsigned prefered_domains;
1034 unsigned allowed_domains;
1035 uint32_t tiling_flags;
1036 uint32_t handle;
1037};
1038
1039struct radeon_cs_chunk { 1059struct radeon_cs_chunk {
1040 uint32_t chunk_id;
1041 uint32_t length_dw; 1060 uint32_t length_dw;
1042 uint32_t *kdata; 1061 uint32_t *kdata;
1043 void __user *user_ptr; 1062 void __user *user_ptr;
@@ -1055,16 +1074,15 @@ struct radeon_cs_parser {
1055 unsigned idx; 1074 unsigned idx;
1056 /* relocations */ 1075 /* relocations */
1057 unsigned nrelocs; 1076 unsigned nrelocs;
1058 struct radeon_cs_reloc *relocs; 1077 struct radeon_bo_list *relocs;
1059 struct radeon_cs_reloc **relocs_ptr; 1078 struct radeon_bo_list *vm_bos;
1060 struct radeon_cs_reloc *vm_bos;
1061 struct list_head validated; 1079 struct list_head validated;
1062 unsigned dma_reloc_idx; 1080 unsigned dma_reloc_idx;
1063 /* indices of various chunks */ 1081 /* indices of various chunks */
1064 int chunk_ib_idx; 1082 struct radeon_cs_chunk *chunk_ib;
1065 int chunk_relocs_idx; 1083 struct radeon_cs_chunk *chunk_relocs;
1066 int chunk_flags_idx; 1084 struct radeon_cs_chunk *chunk_flags;
1067 int chunk_const_ib_idx; 1085 struct radeon_cs_chunk *chunk_const_ib;
1068 struct radeon_ib ib; 1086 struct radeon_ib ib;
1069 struct radeon_ib const_ib; 1087 struct radeon_ib const_ib;
1070 void *track; 1088 void *track;
@@ -1078,7 +1096,7 @@ struct radeon_cs_parser {
1078 1096
1079static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx) 1097static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)
1080{ 1098{
1081 struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx]; 1099 struct radeon_cs_chunk *ibc = p->chunk_ib;
1082 1100
1083 if (ibc->kdata) 1101 if (ibc->kdata)
1084 return ibc->kdata[idx]; 1102 return ibc->kdata[idx];
@@ -1490,6 +1508,10 @@ struct radeon_dpm_fan {
1490 u8 t_hyst; 1508 u8 t_hyst;
1491 u32 cycle_delay; 1509 u32 cycle_delay;
1492 u16 t_max; 1510 u16 t_max;
1511 u8 control_mode;
1512 u16 default_max_fan_pwm;
1513 u16 default_fan_output_sensitivity;
1514 u16 fan_output_sensitivity;
1493 bool ucode_fan_control; 1515 bool ucode_fan_control;
1494}; 1516};
1495 1517
@@ -1623,6 +1645,11 @@ struct radeon_pm {
1623 /* internal thermal controller on rv6xx+ */ 1645 /* internal thermal controller on rv6xx+ */
1624 enum radeon_int_thermal_type int_thermal_type; 1646 enum radeon_int_thermal_type int_thermal_type;
1625 struct device *int_hwmon_dev; 1647 struct device *int_hwmon_dev;
1648 /* fan control parameters */
1649 bool no_fan;
1650 u8 fan_pulses_per_revolution;
1651 u8 fan_min_rpm;
1652 u8 fan_max_rpm;
1626 /* dpm */ 1653 /* dpm */
1627 bool dpm_enabled; 1654 bool dpm_enabled;
1628 struct radeon_dpm dpm; 1655 struct radeon_dpm dpm;
@@ -1785,7 +1812,8 @@ struct radeon_asic_ring {
1785 void (*hdp_flush)(struct radeon_device *rdev, struct radeon_ring *ring); 1812 void (*hdp_flush)(struct radeon_device *rdev, struct radeon_ring *ring);
1786 bool (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp, 1813 bool (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp,
1787 struct radeon_semaphore *semaphore, bool emit_wait); 1814 struct radeon_semaphore *semaphore, bool emit_wait);
1788 void (*vm_flush)(struct radeon_device *rdev, int ridx, struct radeon_vm *vm); 1815 void (*vm_flush)(struct radeon_device *rdev, struct radeon_ring *ring,
1816 unsigned vm_id, uint64_t pd_addr);
1789 1817
1790 /* testing functions */ 1818 /* testing functions */
1791 int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp); 1819 int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp);
@@ -2388,6 +2416,8 @@ struct radeon_device {
2388 struct radeon_atcs atcs; 2416 struct radeon_atcs atcs;
2389 /* srbm instance registers */ 2417 /* srbm instance registers */
2390 struct mutex srbm_mutex; 2418 struct mutex srbm_mutex;
2419 /* GRBM index mutex. Protects concurrents access to GRBM index */
2420 struct mutex grbm_idx_mutex;
2391 /* clock, powergating flags */ 2421 /* clock, powergating flags */
2392 u32 cg_flags; 2422 u32 cg_flags;
2393 u32 pg_flags; 2423 u32 pg_flags;
@@ -2400,6 +2430,10 @@ struct radeon_device {
2400 u64 vram_pin_size; 2430 u64 vram_pin_size;
2401 u64 gart_pin_size; 2431 u64 gart_pin_size;
2402 2432
2433 /* amdkfd interface */
2434 struct kfd_dev *kfd;
2435 struct radeon_sa_manager kfd_bo;
2436
2403 struct mutex mn_lock; 2437 struct mutex mn_lock;
2404 DECLARE_HASHTABLE(mn_hash, 7); 2438 DECLARE_HASHTABLE(mn_hash, 7);
2405}; 2439};
@@ -2831,7 +2865,7 @@ static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v)
2831#define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_execute((rdev), (ib)) 2865#define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_execute((rdev), (ib))
2832#define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_parse((rdev), (ib)) 2866#define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)]->ib_parse((rdev), (ib))
2833#define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)]->is_lockup((rdev), (cp)) 2867#define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)]->is_lockup((rdev), (cp))
2834#define radeon_ring_vm_flush(rdev, r, vm) (rdev)->asic->ring[(r)]->vm_flush((rdev), (r), (vm)) 2868#define radeon_ring_vm_flush(rdev, r, vm_id, pd_addr) (rdev)->asic->ring[(r)->idx]->vm_flush((rdev), (r), (vm_id), (pd_addr))
2835#define radeon_ring_get_rptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_rptr((rdev), (r)) 2869#define radeon_ring_get_rptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_rptr((rdev), (r))
2836#define radeon_ring_get_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_wptr((rdev), (r)) 2870#define radeon_ring_get_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->get_wptr((rdev), (r))
2837#define radeon_ring_set_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->set_wptr((rdev), (r)) 2871#define radeon_ring_set_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->set_wptr((rdev), (r))
@@ -2940,14 +2974,14 @@ int radeon_vm_manager_init(struct radeon_device *rdev);
2940void radeon_vm_manager_fini(struct radeon_device *rdev); 2974void radeon_vm_manager_fini(struct radeon_device *rdev);
2941int radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm); 2975int radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm);
2942void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm); 2976void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm);
2943struct radeon_cs_reloc *radeon_vm_get_bos(struct radeon_device *rdev, 2977struct radeon_bo_list *radeon_vm_get_bos(struct radeon_device *rdev,
2944 struct radeon_vm *vm, 2978 struct radeon_vm *vm,
2945 struct list_head *head); 2979 struct list_head *head);
2946struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev, 2980struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev,
2947 struct radeon_vm *vm, int ring); 2981 struct radeon_vm *vm, int ring);
2948void radeon_vm_flush(struct radeon_device *rdev, 2982void radeon_vm_flush(struct radeon_device *rdev,
2949 struct radeon_vm *vm, 2983 struct radeon_vm *vm,
2950 int ring); 2984 int ring, struct radeon_fence *fence);
2951void radeon_vm_fence(struct radeon_device *rdev, 2985void radeon_vm_fence(struct radeon_device *rdev,
2952 struct radeon_vm *vm, 2986 struct radeon_vm *vm,
2953 struct radeon_fence *fence); 2987 struct radeon_fence *fence);
@@ -3054,7 +3088,7 @@ bool radeon_cs_packet_next_is_pkt3_nop(struct radeon_cs_parser *p);
3054void radeon_cs_dump_packet(struct radeon_cs_parser *p, 3088void radeon_cs_dump_packet(struct radeon_cs_parser *p,
3055 struct radeon_cs_packet *pkt); 3089 struct radeon_cs_packet *pkt);
3056int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p, 3090int radeon_cs_packet_next_reloc(struct radeon_cs_parser *p,
3057 struct radeon_cs_reloc **cs_reloc, 3091 struct radeon_bo_list **cs_reloc,
3058 int nomm); 3092 int nomm);
3059int r600_cs_common_vline_parse(struct radeon_cs_parser *p, 3093int r600_cs_common_vline_parse(struct radeon_cs_parser *p,
3060 uint32_t *vline_start_end, 3094 uint32_t *vline_start_end,