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-rw-r--r--drivers/gpu/drm/radeon/radeon.h149
1 files changed, 87 insertions, 62 deletions
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index 224506a2f7b1..f3deb4982b2d 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -28,8 +28,6 @@
28#ifndef __RADEON_H__ 28#ifndef __RADEON_H__
29#define __RADEON_H__ 29#define __RADEON_H__
30 30
31#include "radeon_object.h"
32
33/* TODO: Here are things that needs to be done : 31/* TODO: Here are things that needs to be done :
34 * - surface allocator & initializer : (bit like scratch reg) should 32 * - surface allocator & initializer : (bit like scratch reg) should
35 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings 33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
@@ -67,6 +65,11 @@
67#include <linux/list.h> 65#include <linux/list.h>
68#include <linux/kref.h> 66#include <linux/kref.h>
69 67
68#include <ttm/ttm_bo_api.h>
69#include <ttm/ttm_bo_driver.h>
70#include <ttm/ttm_placement.h>
71#include <ttm/ttm_module.h>
72
70#include "radeon_family.h" 73#include "radeon_family.h"
71#include "radeon_mode.h" 74#include "radeon_mode.h"
72#include "radeon_reg.h" 75#include "radeon_reg.h"
@@ -186,76 +189,60 @@ void radeon_fence_unref(struct radeon_fence **fence);
186 * Tiling registers 189 * Tiling registers
187 */ 190 */
188struct radeon_surface_reg { 191struct radeon_surface_reg {
189 struct radeon_object *robj; 192 struct radeon_bo *bo;
190}; 193};
191 194
192#define RADEON_GEM_MAX_SURFACES 8 195#define RADEON_GEM_MAX_SURFACES 8
193 196
194/* 197/*
195 * Radeon buffer. 198 * TTM.
196 */ 199 */
197struct radeon_object; 200struct radeon_mman {
201 struct ttm_bo_global_ref bo_global_ref;
202 struct ttm_global_reference mem_global_ref;
203 bool mem_global_referenced;
204 struct ttm_bo_device bdev;
205};
206
207struct radeon_bo {
208 /* Protected by gem.mutex */
209 struct list_head list;
210 /* Protected by tbo.reserved */
211 struct ttm_buffer_object tbo;
212 struct ttm_bo_kmap_obj kmap;
213 unsigned pin_count;
214 void *kptr;
215 u32 tiling_flags;
216 u32 pitch;
217 int surface_reg;
218 /* Constant after initialization */
219 struct radeon_device *rdev;
220 struct drm_gem_object *gobj;
221};
198 222
199struct radeon_object_list { 223struct radeon_bo_list {
200 struct list_head list; 224 struct list_head list;
201 struct radeon_object *robj; 225 struct radeon_bo *bo;
202 uint64_t gpu_offset; 226 uint64_t gpu_offset;
203 unsigned rdomain; 227 unsigned rdomain;
204 unsigned wdomain; 228 unsigned wdomain;
205 uint32_t tiling_flags; 229 u32 tiling_flags;
206}; 230};
207 231
208int radeon_object_init(struct radeon_device *rdev);
209void radeon_object_fini(struct radeon_device *rdev);
210int radeon_object_create(struct radeon_device *rdev,
211 struct drm_gem_object *gobj,
212 unsigned long size,
213 bool kernel,
214 uint32_t domain,
215 bool interruptible,
216 struct radeon_object **robj_ptr);
217int radeon_object_kmap(struct radeon_object *robj, void **ptr);
218void radeon_object_kunmap(struct radeon_object *robj);
219void radeon_object_unref(struct radeon_object **robj);
220int radeon_object_pin(struct radeon_object *robj, uint32_t domain,
221 uint64_t *gpu_addr);
222void radeon_object_unpin(struct radeon_object *robj);
223int radeon_object_wait(struct radeon_object *robj);
224int radeon_object_busy_domain(struct radeon_object *robj, uint32_t *cur_placement);
225int radeon_object_evict_vram(struct radeon_device *rdev);
226int radeon_object_mmap(struct radeon_object *robj, uint64_t *offset);
227void radeon_object_force_delete(struct radeon_device *rdev);
228void radeon_object_list_add_object(struct radeon_object_list *lobj,
229 struct list_head *head);
230int radeon_object_list_validate(struct list_head *head, void *fence);
231void radeon_object_list_unvalidate(struct list_head *head);
232void radeon_object_list_clean(struct list_head *head);
233int radeon_object_fbdev_mmap(struct radeon_object *robj,
234 struct vm_area_struct *vma);
235unsigned long radeon_object_size(struct radeon_object *robj);
236void radeon_object_clear_surface_reg(struct radeon_object *robj);
237int radeon_object_check_tiling(struct radeon_object *robj, bool has_moved,
238 bool force_drop);
239void radeon_object_set_tiling_flags(struct radeon_object *robj,
240 uint32_t tiling_flags, uint32_t pitch);
241void radeon_object_get_tiling_flags(struct radeon_object *robj, uint32_t *tiling_flags, uint32_t *pitch);
242void radeon_bo_move_notify(struct ttm_buffer_object *bo,
243 struct ttm_mem_reg *mem);
244void radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo);
245/* 232/*
246 * GEM objects. 233 * GEM objects.
247 */ 234 */
248struct radeon_gem { 235struct radeon_gem {
236 struct mutex mutex;
249 struct list_head objects; 237 struct list_head objects;
250}; 238};
251 239
252int radeon_gem_init(struct radeon_device *rdev); 240int radeon_gem_init(struct radeon_device *rdev);
253void radeon_gem_fini(struct radeon_device *rdev); 241void radeon_gem_fini(struct radeon_device *rdev);
254int radeon_gem_object_create(struct radeon_device *rdev, int size, 242int radeon_gem_object_create(struct radeon_device *rdev, int size,
255 int alignment, int initial_domain, 243 int alignment, int initial_domain,
256 bool discardable, bool kernel, 244 bool discardable, bool kernel,
257 bool interruptible, 245 struct drm_gem_object **obj);
258 struct drm_gem_object **obj);
259int radeon_gem_object_pin(struct drm_gem_object *obj, uint32_t pin_domain, 246int radeon_gem_object_pin(struct drm_gem_object *obj, uint32_t pin_domain,
260 uint64_t *gpu_addr); 247 uint64_t *gpu_addr);
261void radeon_gem_object_unpin(struct drm_gem_object *obj); 248void radeon_gem_object_unpin(struct drm_gem_object *obj);
@@ -271,7 +258,7 @@ struct radeon_gart_table_ram {
271}; 258};
272 259
273struct radeon_gart_table_vram { 260struct radeon_gart_table_vram {
274 struct radeon_object *robj; 261 struct radeon_bo *robj;
275 volatile uint32_t *ptr; 262 volatile uint32_t *ptr;
276}; 263};
277 264
@@ -352,11 +339,14 @@ struct radeon_irq {
352 bool sw_int; 339 bool sw_int;
353 /* FIXME: use a define max crtc rather than hardcode it */ 340 /* FIXME: use a define max crtc rather than hardcode it */
354 bool crtc_vblank_int[2]; 341 bool crtc_vblank_int[2];
342 spinlock_t sw_lock;
343 int sw_refcount;
355}; 344};
356 345
357int radeon_irq_kms_init(struct radeon_device *rdev); 346int radeon_irq_kms_init(struct radeon_device *rdev);
358void radeon_irq_kms_fini(struct radeon_device *rdev); 347void radeon_irq_kms_fini(struct radeon_device *rdev);
359 348void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev);
349void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev);
360 350
361/* 351/*
362 * CP & ring. 352 * CP & ring.
@@ -376,7 +366,7 @@ struct radeon_ib {
376 */ 366 */
377struct radeon_ib_pool { 367struct radeon_ib_pool {
378 struct mutex mutex; 368 struct mutex mutex;
379 struct radeon_object *robj; 369 struct radeon_bo *robj;
380 struct list_head scheduled_ibs; 370 struct list_head scheduled_ibs;
381 struct radeon_ib ibs[RADEON_IB_POOL_SIZE]; 371 struct radeon_ib ibs[RADEON_IB_POOL_SIZE];
382 bool ready; 372 bool ready;
@@ -384,7 +374,7 @@ struct radeon_ib_pool {
384}; 374};
385 375
386struct radeon_cp { 376struct radeon_cp {
387 struct radeon_object *ring_obj; 377 struct radeon_bo *ring_obj;
388 volatile uint32_t *ring; 378 volatile uint32_t *ring;
389 unsigned rptr; 379 unsigned rptr;
390 unsigned wptr; 380 unsigned wptr;
@@ -399,8 +389,25 @@ struct radeon_cp {
399 bool ready; 389 bool ready;
400}; 390};
401 391
392/*
393 * R6xx+ IH ring
394 */
395struct r600_ih {
396 struct radeon_bo *ring_obj;
397 volatile uint32_t *ring;
398 unsigned rptr;
399 unsigned wptr;
400 unsigned wptr_old;
401 unsigned ring_size;
402 uint64_t gpu_addr;
403 uint32_t align_mask;
404 uint32_t ptr_mask;
405 spinlock_t lock;
406 bool enabled;
407};
408
402struct r600_blit { 409struct r600_blit {
403 struct radeon_object *shader_obj; 410 struct radeon_bo *shader_obj;
404 u64 shader_gpu_addr; 411 u64 shader_gpu_addr;
405 u32 vs_offset, ps_offset; 412 u32 vs_offset, ps_offset;
406 u32 state_offset; 413 u32 state_offset;
@@ -430,8 +437,8 @@ void radeon_ring_fini(struct radeon_device *rdev);
430 */ 437 */
431struct radeon_cs_reloc { 438struct radeon_cs_reloc {
432 struct drm_gem_object *gobj; 439 struct drm_gem_object *gobj;
433 struct radeon_object *robj; 440 struct radeon_bo *robj;
434 struct radeon_object_list lobj; 441 struct radeon_bo_list lobj;
435 uint32_t handle; 442 uint32_t handle;
436 uint32_t flags; 443 uint32_t flags;
437}; 444};
@@ -527,7 +534,7 @@ void radeon_agp_fini(struct radeon_device *rdev);
527 * Writeback 534 * Writeback
528 */ 535 */
529struct radeon_wb { 536struct radeon_wb {
530 struct radeon_object *wb_obj; 537 struct radeon_bo *wb_obj;
531 volatile uint32_t *wb; 538 volatile uint32_t *wb;
532 uint64_t gpu_addr; 539 uint64_t gpu_addr;
533}; 540};
@@ -639,6 +646,7 @@ struct radeon_asic {
639 uint32_t offset, uint32_t obj_size); 646 uint32_t offset, uint32_t obj_size);
640 int (*clear_surface_reg)(struct radeon_device *rdev, int reg); 647 int (*clear_surface_reg)(struct radeon_device *rdev, int reg);
641 void (*bandwidth_update)(struct radeon_device *rdev); 648 void (*bandwidth_update)(struct radeon_device *rdev);
649 void (*hdp_flush)(struct radeon_device *rdev);
642}; 650};
643 651
644/* 652/*
@@ -751,9 +759,9 @@ struct radeon_device {
751 uint8_t *bios; 759 uint8_t *bios;
752 bool is_atom_bios; 760 bool is_atom_bios;
753 uint16_t bios_header_start; 761 uint16_t bios_header_start;
754 struct radeon_object *stollen_vga_memory; 762 struct radeon_bo *stollen_vga_memory;
755 struct fb_info *fbdev_info; 763 struct fb_info *fbdev_info;
756 struct radeon_object *fbdev_robj; 764 struct radeon_bo *fbdev_rbo;
757 struct radeon_framebuffer *fbdev_rfb; 765 struct radeon_framebuffer *fbdev_rfb;
758 /* Register mmio */ 766 /* Register mmio */
759 resource_size_t rmmio_base; 767 resource_size_t rmmio_base;
@@ -791,8 +799,10 @@ struct radeon_device {
791 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES]; 799 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
792 const struct firmware *me_fw; /* all family ME firmware */ 800 const struct firmware *me_fw; /* all family ME firmware */
793 const struct firmware *pfp_fw; /* r6/700 PFP firmware */ 801 const struct firmware *pfp_fw; /* r6/700 PFP firmware */
802 const struct firmware *rlc_fw; /* r6/700 RLC firmware */
794 struct r600_blit r600_blit; 803 struct r600_blit r600_blit;
795 int msi_enabled; /* msi enabled */ 804 int msi_enabled; /* msi enabled */
805 struct r600_ih ih; /* r6/700 interrupt ring */
796}; 806};
797 807
798int radeon_device_init(struct radeon_device *rdev, 808int radeon_device_init(struct radeon_device *rdev,
@@ -829,6 +839,10 @@ static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32
829 } 839 }
830} 840}
831 841
842/*
843 * Cast helper
844 */
845#define to_radeon_fence(p) ((struct radeon_fence *)(p))
832 846
833/* 847/*
834 * Registers read & write functions. 848 * Registers read & write functions.
@@ -965,18 +979,20 @@ static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v)
965#define radeon_get_engine_clock(rdev) (rdev)->asic->get_engine_clock((rdev)) 979#define radeon_get_engine_clock(rdev) (rdev)->asic->get_engine_clock((rdev))
966#define radeon_set_engine_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e)) 980#define radeon_set_engine_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e))
967#define radeon_get_memory_clock(rdev) (rdev)->asic->get_memory_clock((rdev)) 981#define radeon_get_memory_clock(rdev) (rdev)->asic->get_memory_clock((rdev))
968#define radeon_set_memory_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e)) 982#define radeon_set_memory_clock(rdev, e) (rdev)->asic->set_memory_clock((rdev), (e))
969#define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->set_pcie_lanes((rdev), (l)) 983#define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->set_pcie_lanes((rdev), (l))
970#define radeon_set_clock_gating(rdev, e) (rdev)->asic->set_clock_gating((rdev), (e)) 984#define radeon_set_clock_gating(rdev, e) (rdev)->asic->set_clock_gating((rdev), (e))
971#define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->set_surface_reg((rdev), (r), (f), (p), (o), (s))) 985#define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->set_surface_reg((rdev), (r), (f), (p), (o), (s)))
972#define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->clear_surface_reg((rdev), (r))) 986#define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->clear_surface_reg((rdev), (r)))
973#define radeon_bandwidth_update(rdev) (rdev)->asic->bandwidth_update((rdev)) 987#define radeon_bandwidth_update(rdev) (rdev)->asic->bandwidth_update((rdev))
988#define radeon_hdp_flush(rdev) (rdev)->asic->hdp_flush((rdev))
974 989
975/* Common functions */ 990/* Common functions */
976extern int radeon_gart_table_vram_pin(struct radeon_device *rdev); 991extern int radeon_gart_table_vram_pin(struct radeon_device *rdev);
977extern int radeon_modeset_init(struct radeon_device *rdev); 992extern int radeon_modeset_init(struct radeon_device *rdev);
978extern void radeon_modeset_fini(struct radeon_device *rdev); 993extern void radeon_modeset_fini(struct radeon_device *rdev);
979extern bool radeon_card_posted(struct radeon_device *rdev); 994extern bool radeon_card_posted(struct radeon_device *rdev);
995extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
980extern int radeon_clocks_init(struct radeon_device *rdev); 996extern int radeon_clocks_init(struct radeon_device *rdev);
981extern void radeon_clocks_fini(struct radeon_device *rdev); 997extern void radeon_clocks_fini(struct radeon_device *rdev);
982extern void radeon_scratch_init(struct radeon_device *rdev); 998extern void radeon_scratch_init(struct radeon_device *rdev);
@@ -1021,7 +1037,7 @@ extern int r100_cp_reset(struct radeon_device *rdev);
1021extern void r100_vga_render_disable(struct radeon_device *rdev); 1037extern void r100_vga_render_disable(struct radeon_device *rdev);
1022extern int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p, 1038extern int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
1023 struct radeon_cs_packet *pkt, 1039 struct radeon_cs_packet *pkt,
1024 struct radeon_object *robj); 1040 struct radeon_bo *robj);
1025extern int r100_cs_parse_packet0(struct radeon_cs_parser *p, 1041extern int r100_cs_parse_packet0(struct radeon_cs_parser *p,
1026 struct radeon_cs_packet *pkt, 1042 struct radeon_cs_packet *pkt,
1027 const unsigned *auth, unsigned n, 1043 const unsigned *auth, unsigned n,
@@ -1029,6 +1045,8 @@ extern int r100_cs_parse_packet0(struct radeon_cs_parser *p,
1029extern int r100_cs_packet_parse(struct radeon_cs_parser *p, 1045extern int r100_cs_packet_parse(struct radeon_cs_parser *p,
1030 struct radeon_cs_packet *pkt, 1046 struct radeon_cs_packet *pkt,
1031 unsigned idx); 1047 unsigned idx);
1048extern void r100_enable_bm(struct radeon_device *rdev);
1049extern void r100_set_common_regs(struct radeon_device *rdev);
1032 1050
1033/* rv200,rv250,rv280 */ 1051/* rv200,rv250,rv280 */
1034extern void r200_set_safe_registers(struct radeon_device *rdev); 1052extern void r200_set_safe_registers(struct radeon_device *rdev);
@@ -1104,7 +1122,14 @@ extern void r600_wb_disable(struct radeon_device *rdev);
1104extern void r600_scratch_init(struct radeon_device *rdev); 1122extern void r600_scratch_init(struct radeon_device *rdev);
1105extern int r600_blit_init(struct radeon_device *rdev); 1123extern int r600_blit_init(struct radeon_device *rdev);
1106extern void r600_blit_fini(struct radeon_device *rdev); 1124extern void r600_blit_fini(struct radeon_device *rdev);
1107extern int r600_cp_init_microcode(struct radeon_device *rdev); 1125extern int r600_init_microcode(struct radeon_device *rdev);
1108extern int r600_gpu_reset(struct radeon_device *rdev); 1126extern int r600_gpu_reset(struct radeon_device *rdev);
1127/* r600 irq */
1128extern int r600_irq_init(struct radeon_device *rdev);
1129extern void r600_irq_fini(struct radeon_device *rdev);
1130extern void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size);
1131extern int r600_irq_set(struct radeon_device *rdev);
1132
1133#include "radeon_object.h"
1109 1134
1110#endif 1135#endif