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path: root/drivers/gpu/drm/radeon/radeon.h
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Diffstat (limited to 'drivers/gpu/drm/radeon/radeon.h')
-rw-r--r--drivers/gpu/drm/radeon/radeon.h109
1 files changed, 36 insertions, 73 deletions
diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index c1e056b35b29..e3170c794c1d 100644
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -102,7 +102,7 @@ extern int radeon_pcie_gen2;
102#define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2) 102#define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2)
103/* RADEON_IB_POOL_SIZE must be a power of 2 */ 103/* RADEON_IB_POOL_SIZE must be a power of 2 */
104#define RADEON_IB_POOL_SIZE 16 104#define RADEON_IB_POOL_SIZE 16
105#define RADEON_DEBUGFS_MAX_NUM_FILES 32 105#define RADEON_DEBUGFS_MAX_COMPONENTS 32
106#define RADEONFB_CONN_LIMIT 4 106#define RADEONFB_CONN_LIMIT 4
107#define RADEON_BIOS_NUM_SCRATCH 8 107#define RADEON_BIOS_NUM_SCRATCH 8
108 108
@@ -523,9 +523,30 @@ struct r600_ih {
523 bool enabled; 523 bool enabled;
524}; 524};
525 525
526struct r600_blit_cp_primitives {
527 void (*set_render_target)(struct radeon_device *rdev, int format,
528 int w, int h, u64 gpu_addr);
529 void (*cp_set_surface_sync)(struct radeon_device *rdev,
530 u32 sync_type, u32 size,
531 u64 mc_addr);
532 void (*set_shaders)(struct radeon_device *rdev);
533 void (*set_vtx_resource)(struct radeon_device *rdev, u64 gpu_addr);
534 void (*set_tex_resource)(struct radeon_device *rdev,
535 int format, int w, int h, int pitch,
536 u64 gpu_addr);
537 void (*set_scissors)(struct radeon_device *rdev, int x1, int y1,
538 int x2, int y2);
539 void (*draw_auto)(struct radeon_device *rdev);
540 void (*set_default_state)(struct radeon_device *rdev);
541};
542
526struct r600_blit { 543struct r600_blit {
527 struct mutex mutex; 544 struct mutex mutex;
528 struct radeon_bo *shader_obj; 545 struct radeon_bo *shader_obj;
546 struct r600_blit_cp_primitives primitives;
547 int max_dim;
548 int ring_size_common;
549 int ring_size_per_loop;
529 u64 shader_gpu_addr; 550 u64 shader_gpu_addr;
530 u32 vs_offset, ps_offset; 551 u32 vs_offset, ps_offset;
531 u32 state_offset; 552 u32 state_offset;
@@ -534,6 +555,8 @@ struct r600_blit {
534 struct radeon_ib *vb_ib; 555 struct radeon_ib *vb_ib;
535}; 556};
536 557
558void r600_blit_suspend(struct radeon_device *rdev);
559
537int radeon_ib_get(struct radeon_device *rdev, struct radeon_ib **ib); 560int radeon_ib_get(struct radeon_device *rdev, struct radeon_ib **ib);
538void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib); 561void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib);
539int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib); 562int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib);
@@ -601,32 +624,7 @@ struct radeon_cs_parser {
601 624
602extern int radeon_cs_update_pages(struct radeon_cs_parser *p, int pg_idx); 625extern int radeon_cs_update_pages(struct radeon_cs_parser *p, int pg_idx);
603extern int radeon_cs_finish_pages(struct radeon_cs_parser *p); 626extern int radeon_cs_finish_pages(struct radeon_cs_parser *p);
604 627extern u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx);
605
606static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)
607{
608 struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
609 u32 pg_idx, pg_offset;
610 u32 idx_value = 0;
611 int new_page;
612
613 pg_idx = (idx * 4) / PAGE_SIZE;
614 pg_offset = (idx * 4) % PAGE_SIZE;
615
616 if (ibc->kpage_idx[0] == pg_idx)
617 return ibc->kpage[0][pg_offset/4];
618 if (ibc->kpage_idx[1] == pg_idx)
619 return ibc->kpage[1][pg_offset/4];
620
621 new_page = radeon_cs_update_pages(p, pg_idx);
622 if (new_page < 0) {
623 p->parser_error = new_page;
624 return 0;
625 }
626
627 idx_value = ibc->kpage[new_page][pg_offset/4];
628 return idx_value;
629}
630 628
631struct radeon_cs_packet { 629struct radeon_cs_packet {
632 unsigned idx; 630 unsigned idx;
@@ -869,7 +867,7 @@ struct radeon_pm {
869/* 867/*
870 * Benchmarking 868 * Benchmarking
871 */ 869 */
872void radeon_benchmark(struct radeon_device *rdev); 870void radeon_benchmark(struct radeon_device *rdev, int test_number);
873 871
874 872
875/* 873/*
@@ -1252,45 +1250,10 @@ int radeon_device_init(struct radeon_device *rdev,
1252void radeon_device_fini(struct radeon_device *rdev); 1250void radeon_device_fini(struct radeon_device *rdev);
1253int radeon_gpu_wait_for_idle(struct radeon_device *rdev); 1251int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
1254 1252
1255static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg) 1253uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg);
1256{ 1254void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
1257 if (reg < rdev->rmmio_size) 1255u32 r100_io_rreg(struct radeon_device *rdev, u32 reg);
1258 return readl((rdev->rmmio) + reg); 1256void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v);
1259 else {
1260 writel(reg, (rdev->rmmio) + RADEON_MM_INDEX);
1261 return readl((rdev->rmmio) + RADEON_MM_DATA);
1262 }
1263}
1264
1265static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
1266{
1267 if (reg < rdev->rmmio_size)
1268 writel(v, (rdev->rmmio) + reg);
1269 else {
1270 writel(reg, (rdev->rmmio) + RADEON_MM_INDEX);
1271 writel(v, (rdev->rmmio) + RADEON_MM_DATA);
1272 }
1273}
1274
1275static inline u32 r100_io_rreg(struct radeon_device *rdev, u32 reg)
1276{
1277 if (reg < rdev->rio_mem_size)
1278 return ioread32(rdev->rio_mem + reg);
1279 else {
1280 iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX);
1281 return ioread32(rdev->rio_mem + RADEON_MM_DATA);
1282 }
1283}
1284
1285static inline void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v)
1286{
1287 if (reg < rdev->rio_mem_size)
1288 iowrite32(v, rdev->rio_mem + reg);
1289 else {
1290 iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX);
1291 iowrite32(v, rdev->rio_mem + RADEON_MM_DATA);
1292 }
1293}
1294 1257
1295/* 1258/*
1296 * Cast helper 1259 * Cast helper
@@ -1413,19 +1376,19 @@ void radeon_atombios_fini(struct radeon_device *rdev);
1413/* 1376/*
1414 * RING helpers. 1377 * RING helpers.
1415 */ 1378 */
1379
1380#if DRM_DEBUG_CODE == 0
1416static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v) 1381static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v)
1417{ 1382{
1418#if DRM_DEBUG_CODE
1419 if (rdev->cp.count_dw <= 0) {
1420 DRM_ERROR("radeon: writting more dword to ring than expected !\n");
1421 }
1422#endif
1423 rdev->cp.ring[rdev->cp.wptr++] = v; 1383 rdev->cp.ring[rdev->cp.wptr++] = v;
1424 rdev->cp.wptr &= rdev->cp.ptr_mask; 1384 rdev->cp.wptr &= rdev->cp.ptr_mask;
1425 rdev->cp.count_dw--; 1385 rdev->cp.count_dw--;
1426 rdev->cp.ring_free_dw--; 1386 rdev->cp.ring_free_dw--;
1427} 1387}
1428 1388#else
1389/* With debugging this is just too big to inline */
1390void radeon_ring_write(struct radeon_device *rdev, uint32_t v);
1391#endif
1429 1392
1430/* 1393/*
1431 * ASICs macro. 1394 * ASICs macro.