1 files changed, 63 insertions, 7 deletions
diff --git a/drivers/gpu/drm/radeon/r600_cs.c b/drivers/gpu/drm/radeon/r600_cs.c
index cd2c63bce501..c39c1bc13016 100644
--- a/drivers/gpu/drm/radeon/r600_cs.c
+++ b/drivers/gpu/drm/radeon/r600_cs.c
@@ -45,6 +45,7 @@ struct r600_cs_track {
        u32                     nbanks;
        u32                     npipes;
        /* value we track */
+        u32                     sq_config;
        u32                     nsamples;
        u32                     cb_color_base_last[8];
        struct radeon_bo        *cb_color_bo[8];
@@ -141,6 +142,8 @@ static void r600_cs_track_init(struct r600_cs_track *track)
 {
        int i;
+        /* assume DX9 mode */
+        track->sq_config = DX9_CONSTS;
        for (i = 0; i < 8; i++) {
                track->cb_color_base_last[i] = 0;
                track->cb_color_size[i] = 0;
@@ -715,6 +718,9 @@ static inline int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx
                tmp =radeon_get_ib_value(p, idx);
                ib[idx] = 0;
                break;
+        case SQ_CONFIG:
+                track->sq_config = radeon_get_ib_value(p, idx);
+                break;
        case R_028800_DB_DEPTH_CONTROL:
                track->db_depth_control = radeon_get_ib_value(p, idx);
                break;
@@ -869,6 +875,54 @@ static inline int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx
        case SQ_PGM_START_VS:
        case SQ_PGM_START_GS:
        case SQ_PGM_START_PS:
+        case SQ_ALU_CONST_CACHE_GS_0:
+        case SQ_ALU_CONST_CACHE_GS_1:
+        case SQ_ALU_CONST_CACHE_GS_2:
+        case SQ_ALU_CONST_CACHE_GS_3:
+        case SQ_ALU_CONST_CACHE_GS_4:
+        case SQ_ALU_CONST_CACHE_GS_5:
+        case SQ_ALU_CONST_CACHE_GS_6:
+        case SQ_ALU_CONST_CACHE_GS_7:
+        case SQ_ALU_CONST_CACHE_GS_8:
+        case SQ_ALU_CONST_CACHE_GS_9:
+        case SQ_ALU_CONST_CACHE_GS_10:
+        case SQ_ALU_CONST_CACHE_GS_11:
+        case SQ_ALU_CONST_CACHE_GS_12:
+        case SQ_ALU_CONST_CACHE_GS_13:
+        case SQ_ALU_CONST_CACHE_GS_14:
+        case SQ_ALU_CONST_CACHE_GS_15:
+        case SQ_ALU_CONST_CACHE_PS_0:
+        case SQ_ALU_CONST_CACHE_PS_1:
+        case SQ_ALU_CONST_CACHE_PS_2:
+        case SQ_ALU_CONST_CACHE_PS_3:
+        case SQ_ALU_CONST_CACHE_PS_4:
+        case SQ_ALU_CONST_CACHE_PS_5:
+        case SQ_ALU_CONST_CACHE_PS_6:
+        case SQ_ALU_CONST_CACHE_PS_7:
+        case SQ_ALU_CONST_CACHE_PS_8:
+        case SQ_ALU_CONST_CACHE_PS_9:
+        case SQ_ALU_CONST_CACHE_PS_10:
+        case SQ_ALU_CONST_CACHE_PS_11:
+        case SQ_ALU_CONST_CACHE_PS_12:
+        case SQ_ALU_CONST_CACHE_PS_13:
+        case SQ_ALU_CONST_CACHE_PS_14:
+        case SQ_ALU_CONST_CACHE_PS_15:
+        case SQ_ALU_CONST_CACHE_VS_0:
+        case SQ_ALU_CONST_CACHE_VS_1:
+        case SQ_ALU_CONST_CACHE_VS_2:
+        case SQ_ALU_CONST_CACHE_VS_3:
+        case SQ_ALU_CONST_CACHE_VS_4:
+        case SQ_ALU_CONST_CACHE_VS_5:
+        case SQ_ALU_CONST_CACHE_VS_6:
+        case SQ_ALU_CONST_CACHE_VS_7:
+        case SQ_ALU_CONST_CACHE_VS_8:
+        case SQ_ALU_CONST_CACHE_VS_9:
+        case SQ_ALU_CONST_CACHE_VS_10:
+        case SQ_ALU_CONST_CACHE_VS_11:
+        case SQ_ALU_CONST_CACHE_VS_12:
+        case SQ_ALU_CONST_CACHE_VS_13:
+        case SQ_ALU_CONST_CACHE_VS_14:
+        case SQ_ALU_CONST_CACHE_VS_15:
                r = r600_cs_packet_next_reloc(p, &reloc);
                if (r) {
                        dev_warn(p->dev, "bad SET_CONTEXT_REG "
@@ -1226,13 +1280,15 @@ static int r600_packet3_check(struct radeon_cs_parser *p,
                }
                break;
        case PACKET3_SET_ALU_CONST:
-                start_reg = (idx_value << 2) + PACKET3_SET_ALU_CONST_OFFSET;
+                if (track->sq_config & DX9_CONSTS) {
-                end_reg = 4 * pkt->count + start_reg - 4;
+                        start_reg = (idx_value << 2) + PACKET3_SET_ALU_CONST_OFFSET;
-                if ((start_reg < PACKET3_SET_ALU_CONST_OFFSET) ||
+                        end_reg = 4 * pkt->count + start_reg - 4;
-                    (start_reg >= PACKET3_SET_ALU_CONST_END) ||
+                        if ((start_reg < PACKET3_SET_ALU_CONST_OFFSET) ||
-                    (end_reg >= PACKET3_SET_ALU_CONST_END)) {
+                            (start_reg >= PACKET3_SET_ALU_CONST_END) ||
-                        DRM_ERROR("bad SET_ALU_CONST\n");
+                            (end_reg >= PACKET3_SET_ALU_CONST_END)) {
-                        return -EINVAL;
+                                DRM_ERROR("bad SET_ALU_CONST\n");
+                                return -EINVAL;
+                        }
                }
                break;
        case PACKET3_SET_BOOL_CONST:

diff --git a/drivers/gpu/drm/radeon/r600_cs.c b/drivers/gpu/drm/radeon/r600_cs.c index cd2c63bce501..c39c1bc13016 100644 --- a/drivers/gpu/drm/radeon/r600_cs.c +++ b/drivers/gpu/drm/radeon/r600_cs.c
@@ -45,6 +45,7 @@ struct r600_cs_track {
45	u32 nbanks;	45	u32 nbanks;
46	u32 npipes;	46	u32 npipes;
47	/* value we track */	47	/* value we track */
		48	u32 sq_config;
48	u32 nsamples;	49	u32 nsamples;
49	u32 cb_color_base_last[8];	50	u32 cb_color_base_last[8];
50	struct radeon_bo *cb_color_bo[8];	51	struct radeon_bo *cb_color_bo[8];
@@ -141,6 +142,8 @@ static void r600_cs_track_init(struct r600_cs_track *track)
141	{	142	{
142	int i;	143	int i;
143		144
		145	/* assume DX9 mode */
		146	track->sq_config = DX9_CONSTS;
144	for (i = 0; i < 8; i++) {	147	for (i = 0; i < 8; i++) {
145	track->cb_color_base_last[i] = 0;	148	track->cb_color_base_last[i] = 0;
146	track->cb_color_size[i] = 0;	149	track->cb_color_size[i] = 0;
@@ -715,6 +718,9 @@ static inline int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx
715	tmp =radeon_get_ib_value(p, idx);	718	tmp =radeon_get_ib_value(p, idx);
716	ib[idx] = 0;	719	ib[idx] = 0;
717	break;	720	break;
		721	case SQ_CONFIG:
		722	track->sq_config = radeon_get_ib_value(p, idx);
		723	break;
718	case R_028800_DB_DEPTH_CONTROL:	724	case R_028800_DB_DEPTH_CONTROL:
719	track->db_depth_control = radeon_get_ib_value(p, idx);	725	track->db_depth_control = radeon_get_ib_value(p, idx);
720	break;	726	break;
@@ -869,6 +875,54 @@ static inline int r600_cs_check_reg(struct radeon_cs_parser *p, u32 reg, u32 idx
869	case SQ_PGM_START_VS:	875	case SQ_PGM_START_VS:
870	case SQ_PGM_START_GS:	876	case SQ_PGM_START_GS:
871	case SQ_PGM_START_PS:	877	case SQ_PGM_START_PS:
		878	case SQ_ALU_CONST_CACHE_GS_0:
		879	case SQ_ALU_CONST_CACHE_GS_1:
		880	case SQ_ALU_CONST_CACHE_GS_2:
		881	case SQ_ALU_CONST_CACHE_GS_3:
		882	case SQ_ALU_CONST_CACHE_GS_4:
		883	case SQ_ALU_CONST_CACHE_GS_5:
		884	case SQ_ALU_CONST_CACHE_GS_6:
		885	case SQ_ALU_CONST_CACHE_GS_7:
		886	case SQ_ALU_CONST_CACHE_GS_8:
		887	case SQ_ALU_CONST_CACHE_GS_9:
		888	case SQ_ALU_CONST_CACHE_GS_10:
		889	case SQ_ALU_CONST_CACHE_GS_11:
		890	case SQ_ALU_CONST_CACHE_GS_12:
		891	case SQ_ALU_CONST_CACHE_GS_13:
		892	case SQ_ALU_CONST_CACHE_GS_14:
		893	case SQ_ALU_CONST_CACHE_GS_15:
		894	case SQ_ALU_CONST_CACHE_PS_0:
		895	case SQ_ALU_CONST_CACHE_PS_1:
		896	case SQ_ALU_CONST_CACHE_PS_2:
		897	case SQ_ALU_CONST_CACHE_PS_3:
		898	case SQ_ALU_CONST_CACHE_PS_4:
		899	case SQ_ALU_CONST_CACHE_PS_5:
		900	case SQ_ALU_CONST_CACHE_PS_6:
		901	case SQ_ALU_CONST_CACHE_PS_7:
		902	case SQ_ALU_CONST_CACHE_PS_8:
		903	case SQ_ALU_CONST_CACHE_PS_9:
		904	case SQ_ALU_CONST_CACHE_PS_10:
		905	case SQ_ALU_CONST_CACHE_PS_11:
		906	case SQ_ALU_CONST_CACHE_PS_12:
		907	case SQ_ALU_CONST_CACHE_PS_13:
		908	case SQ_ALU_CONST_CACHE_PS_14:
		909	case SQ_ALU_CONST_CACHE_PS_15:
		910	case SQ_ALU_CONST_CACHE_VS_0:
		911	case SQ_ALU_CONST_CACHE_VS_1:
		912	case SQ_ALU_CONST_CACHE_VS_2:
		913	case SQ_ALU_CONST_CACHE_VS_3:
		914	case SQ_ALU_CONST_CACHE_VS_4:
		915	case SQ_ALU_CONST_CACHE_VS_5:
		916	case SQ_ALU_CONST_CACHE_VS_6:
		917	case SQ_ALU_CONST_CACHE_VS_7:
		918	case SQ_ALU_CONST_CACHE_VS_8:
		919	case SQ_ALU_CONST_CACHE_VS_9:
		920	case SQ_ALU_CONST_CACHE_VS_10:
		921	case SQ_ALU_CONST_CACHE_VS_11:
		922	case SQ_ALU_CONST_CACHE_VS_12:
		923	case SQ_ALU_CONST_CACHE_VS_13:
		924	case SQ_ALU_CONST_CACHE_VS_14:
		925	case SQ_ALU_CONST_CACHE_VS_15:
872	r = r600_cs_packet_next_reloc(p, &reloc);	926	r = r600_cs_packet_next_reloc(p, &reloc);
873	if (r) {	927	if (r) {
874	dev_warn(p->dev, "bad SET_CONTEXT_REG "	928	dev_warn(p->dev, "bad SET_CONTEXT_REG "
@@ -1226,13 +1280,15 @@ static int r600_packet3_check(struct radeon_cs_parser *p,
1226	}	1280	}
1227	break;	1281	break;
1228	case PACKET3_SET_ALU_CONST:	1282	case PACKET3_SET_ALU_CONST:
1229	start_reg = (idx_value << 2) + PACKET3_SET_ALU_CONST_OFFSET;	1283	if (track->sq_config & DX9_CONSTS) {
1230	end_reg = 4 * pkt->count + start_reg - 4;	1284	start_reg = (idx_value << 2) + PACKET3_SET_ALU_CONST_OFFSET;
1231	if ((start_reg < PACKET3_SET_ALU_CONST_OFFSET) \|\|	1285	end_reg = 4 * pkt->count + start_reg - 4;
1232	(start_reg >= PACKET3_SET_ALU_CONST_END) \|\|	1286	if ((start_reg < PACKET3_SET_ALU_CONST_OFFSET) \|\|
1233	(end_reg >= PACKET3_SET_ALU_CONST_END)) {	1287	(start_reg >= PACKET3_SET_ALU_CONST_END) \|\|
1234	DRM_ERROR("bad SET_ALU_CONST\n");	1288	(end_reg >= PACKET3_SET_ALU_CONST_END)) {
1235	return -EINVAL;	1289	DRM_ERROR("bad SET_ALU_CONST\n");
		1290	return -EINVAL;
		1291	}
1236	}	1292	}
1237	break;	1293	break;
1238	case PACKET3_SET_BOOL_CONST:	1294	case PACKET3_SET_BOOL_CONST: