diff options
Diffstat (limited to 'drivers/gpu/drm/radeon/r600_cs.c')
-rw-r--r-- | drivers/gpu/drm/radeon/r600_cs.c | 46 |
1 files changed, 26 insertions, 20 deletions
diff --git a/drivers/gpu/drm/radeon/r600_cs.c b/drivers/gpu/drm/radeon/r600_cs.c index 7831e0890210..153095fba62f 100644 --- a/drivers/gpu/drm/radeon/r600_cs.c +++ b/drivers/gpu/drm/radeon/r600_cs.c | |||
@@ -295,17 +295,18 @@ static inline int r600_cs_track_validate_cb(struct radeon_cs_parser *p, int i) | |||
295 | } | 295 | } |
296 | 296 | ||
297 | if (!IS_ALIGNED(pitch, pitch_align)) { | 297 | if (!IS_ALIGNED(pitch, pitch_align)) { |
298 | dev_warn(p->dev, "%s:%d cb pitch (%d) invalid\n", | 298 | dev_warn(p->dev, "%s:%d cb pitch (%d, 0x%x, %d) invalid\n", |
299 | __func__, __LINE__, pitch); | 299 | __func__, __LINE__, pitch, pitch_align, array_mode); |
300 | return -EINVAL; | 300 | return -EINVAL; |
301 | } | 301 | } |
302 | if (!IS_ALIGNED(height, height_align)) { | 302 | if (!IS_ALIGNED(height, height_align)) { |
303 | dev_warn(p->dev, "%s:%d cb height (%d) invalid\n", | 303 | dev_warn(p->dev, "%s:%d cb height (%d, 0x%x, %d) invalid\n", |
304 | __func__, __LINE__, height); | 304 | __func__, __LINE__, height, height_align, array_mode); |
305 | return -EINVAL; | 305 | return -EINVAL; |
306 | } | 306 | } |
307 | if (!IS_ALIGNED(base_offset, base_align)) { | 307 | if (!IS_ALIGNED(base_offset, base_align)) { |
308 | dev_warn(p->dev, "%s offset[%d] 0x%llx not aligned\n", __func__, i, base_offset); | 308 | dev_warn(p->dev, "%s offset[%d] 0x%llx 0x%llx, %d not aligned\n", __func__, i, |
309 | base_offset, base_align, array_mode); | ||
309 | return -EINVAL; | 310 | return -EINVAL; |
310 | } | 311 | } |
311 | 312 | ||
@@ -320,7 +321,10 @@ static inline int r600_cs_track_validate_cb(struct radeon_cs_parser *p, int i) | |||
320 | * broken userspace. | 321 | * broken userspace. |
321 | */ | 322 | */ |
322 | } else { | 323 | } else { |
323 | dev_warn(p->dev, "%s offset[%d] %d %d %lu too big\n", __func__, i, track->cb_color_bo_offset[i], tmp, radeon_bo_size(track->cb_color_bo[i])); | 324 | dev_warn(p->dev, "%s offset[%d] %d %d %d %lu too big\n", __func__, i, |
325 | array_mode, | ||
326 | track->cb_color_bo_offset[i], tmp, | ||
327 | radeon_bo_size(track->cb_color_bo[i])); | ||
324 | return -EINVAL; | 328 | return -EINVAL; |
325 | } | 329 | } |
326 | } | 330 | } |
@@ -455,17 +459,18 @@ static int r600_cs_track_check(struct radeon_cs_parser *p) | |||
455 | } | 459 | } |
456 | 460 | ||
457 | if (!IS_ALIGNED(pitch, pitch_align)) { | 461 | if (!IS_ALIGNED(pitch, pitch_align)) { |
458 | dev_warn(p->dev, "%s:%d db pitch (%d) invalid\n", | 462 | dev_warn(p->dev, "%s:%d db pitch (%d, 0x%x, %d) invalid\n", |
459 | __func__, __LINE__, pitch); | 463 | __func__, __LINE__, pitch, pitch_align, array_mode); |
460 | return -EINVAL; | 464 | return -EINVAL; |
461 | } | 465 | } |
462 | if (!IS_ALIGNED(height, height_align)) { | 466 | if (!IS_ALIGNED(height, height_align)) { |
463 | dev_warn(p->dev, "%s:%d db height (%d) invalid\n", | 467 | dev_warn(p->dev, "%s:%d db height (%d, 0x%x, %d) invalid\n", |
464 | __func__, __LINE__, height); | 468 | __func__, __LINE__, height, height_align, array_mode); |
465 | return -EINVAL; | 469 | return -EINVAL; |
466 | } | 470 | } |
467 | if (!IS_ALIGNED(base_offset, base_align)) { | 471 | if (!IS_ALIGNED(base_offset, base_align)) { |
468 | dev_warn(p->dev, "%s offset[%d] 0x%llx not aligned\n", __func__, i, base_offset); | 472 | dev_warn(p->dev, "%s offset[%d] 0x%llx, 0x%llx, %d not aligned\n", __func__, i, |
473 | base_offset, base_align, array_mode); | ||
469 | return -EINVAL; | 474 | return -EINVAL; |
470 | } | 475 | } |
471 | 476 | ||
@@ -473,9 +478,10 @@ static int r600_cs_track_check(struct radeon_cs_parser *p) | |||
473 | nviews = G_028004_SLICE_MAX(track->db_depth_view) + 1; | 478 | nviews = G_028004_SLICE_MAX(track->db_depth_view) + 1; |
474 | tmp = ntiles * bpe * 64 * nviews; | 479 | tmp = ntiles * bpe * 64 * nviews; |
475 | if ((tmp + track->db_offset) > radeon_bo_size(track->db_bo)) { | 480 | if ((tmp + track->db_offset) > radeon_bo_size(track->db_bo)) { |
476 | dev_warn(p->dev, "z/stencil buffer too small (0x%08X %d %d %d -> %u have %lu)\n", | 481 | dev_warn(p->dev, "z/stencil buffer (%d) too small (0x%08X %d %d %d -> %u have %lu)\n", |
477 | track->db_depth_size, ntiles, nviews, bpe, tmp + track->db_offset, | 482 | array_mode, |
478 | radeon_bo_size(track->db_bo)); | 483 | track->db_depth_size, ntiles, nviews, bpe, tmp + track->db_offset, |
484 | radeon_bo_size(track->db_bo)); | ||
479 | return -EINVAL; | 485 | return -EINVAL; |
480 | } | 486 | } |
481 | } | 487 | } |
@@ -1227,18 +1233,18 @@ static inline int r600_check_texture_resource(struct radeon_cs_parser *p, u32 i | |||
1227 | /* XXX check height as well... */ | 1233 | /* XXX check height as well... */ |
1228 | 1234 | ||
1229 | if (!IS_ALIGNED(pitch, pitch_align)) { | 1235 | if (!IS_ALIGNED(pitch, pitch_align)) { |
1230 | dev_warn(p->dev, "%s:%d tex pitch (%d) invalid\n", | 1236 | dev_warn(p->dev, "%s:%d tex pitch (%d, 0x%x, %d) invalid\n", |
1231 | __func__, __LINE__, pitch); | 1237 | __func__, __LINE__, pitch, pitch_align, G_038000_TILE_MODE(word0)); |
1232 | return -EINVAL; | 1238 | return -EINVAL; |
1233 | } | 1239 | } |
1234 | if (!IS_ALIGNED(base_offset, base_align)) { | 1240 | if (!IS_ALIGNED(base_offset, base_align)) { |
1235 | dev_warn(p->dev, "%s:%d tex base offset (0x%llx) invalid\n", | 1241 | dev_warn(p->dev, "%s:%d tex base offset (0x%llx, 0x%llx, %d) invalid\n", |
1236 | __func__, __LINE__, base_offset); | 1242 | __func__, __LINE__, base_offset, base_align, G_038000_TILE_MODE(word0)); |
1237 | return -EINVAL; | 1243 | return -EINVAL; |
1238 | } | 1244 | } |
1239 | if (!IS_ALIGNED(mip_offset, base_align)) { | 1245 | if (!IS_ALIGNED(mip_offset, base_align)) { |
1240 | dev_warn(p->dev, "%s:%d tex mip offset (0x%llx) invalid\n", | 1246 | dev_warn(p->dev, "%s:%d tex mip offset (0x%llx, 0x%llx, %d) invalid\n", |
1241 | __func__, __LINE__, mip_offset); | 1247 | __func__, __LINE__, mip_offset, base_align, G_038000_TILE_MODE(word0)); |
1242 | return -EINVAL; | 1248 | return -EINVAL; |
1243 | } | 1249 | } |
1244 | 1250 | ||