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path: root/drivers/gpu/drm/radeon/r600.c
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Diffstat (limited to 'drivers/gpu/drm/radeon/r600.c')
-rw-r--r--drivers/gpu/drm/radeon/r600.c15
1 files changed, 11 insertions, 4 deletions
diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
index 3cb9d6089373..becb03e8b32f 100644
--- a/drivers/gpu/drm/radeon/r600.c
+++ b/drivers/gpu/drm/radeon/r600.c
@@ -1462,12 +1462,15 @@ u32 r6xx_remap_render_backend(struct radeon_device *rdev,
1462 u32 disabled_rb_mask) 1462 u32 disabled_rb_mask)
1463{ 1463{
1464 u32 rendering_pipe_num, rb_num_width, req_rb_num; 1464 u32 rendering_pipe_num, rb_num_width, req_rb_num;
1465 u32 pipe_rb_ratio, pipe_rb_remain; 1465 u32 pipe_rb_ratio, pipe_rb_remain, tmp;
1466 u32 data = 0, mask = 1 << (max_rb_num - 1); 1466 u32 data = 0, mask = 1 << (max_rb_num - 1);
1467 unsigned i, j; 1467 unsigned i, j;
1468 1468
1469 /* mask out the RBs that don't exist on that asic */ 1469 /* mask out the RBs that don't exist on that asic */
1470 disabled_rb_mask |= (0xff << max_rb_num) & 0xff; 1470 tmp = disabled_rb_mask | ((0xff << max_rb_num) & 0xff);
1471 /* make sure at least one RB is available */
1472 if ((tmp & 0xff) != 0xff)
1473 disabled_rb_mask = tmp;
1471 1474
1472 rendering_pipe_num = 1 << tiling_pipe_num; 1475 rendering_pipe_num = 1 << tiling_pipe_num;
1473 req_rb_num = total_max_rb_num - r600_count_pipe_bits(disabled_rb_mask); 1476 req_rb_num = total_max_rb_num - r600_count_pipe_bits(disabled_rb_mask);
@@ -2313,7 +2316,7 @@ void r600_dma_stop(struct radeon_device *rdev)
2313int r600_dma_resume(struct radeon_device *rdev) 2316int r600_dma_resume(struct radeon_device *rdev)
2314{ 2317{
2315 struct radeon_ring *ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX]; 2318 struct radeon_ring *ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
2316 u32 rb_cntl, dma_cntl; 2319 u32 rb_cntl, dma_cntl, ib_cntl;
2317 u32 rb_bufsz; 2320 u32 rb_bufsz;
2318 int r; 2321 int r;
2319 2322
@@ -2353,7 +2356,11 @@ int r600_dma_resume(struct radeon_device *rdev)
2353 WREG32(DMA_RB_BASE, ring->gpu_addr >> 8); 2356 WREG32(DMA_RB_BASE, ring->gpu_addr >> 8);
2354 2357
2355 /* enable DMA IBs */ 2358 /* enable DMA IBs */
2356 WREG32(DMA_IB_CNTL, DMA_IB_ENABLE); 2359 ib_cntl = DMA_IB_ENABLE;
2360#ifdef __BIG_ENDIAN
2361 ib_cntl |= DMA_IB_SWAP_ENABLE;
2362#endif
2363 WREG32(DMA_IB_CNTL, ib_cntl);
2357 2364
2358 dma_cntl = RREG32(DMA_CNTL); 2365 dma_cntl = RREG32(DMA_CNTL);
2359 dma_cntl &= ~CTXEMPTY_INT_ENABLE; 2366 dma_cntl &= ~CTXEMPTY_INT_ENABLE;