1 files changed, 12 insertions, 8 deletions

diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
index 647ef4079217..bbc189fd3ddc 100644
--- a/drivers/gpu/drm/radeon/r600.c
+++ b/drivers/gpu/drm/radeon/r600.c
@@ -1748,11 +1748,9 @@ bool r600_gfx_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring)
         if (!(reset_mask & (RADEON_RESET_GFX |
                             RADEON_RESET_COMPUTE |
                             RADEON_RESET_CP))) {
-                radeon_ring_lockup_update(ring);
+                radeon_ring_lockup_update(rdev, ring);
                 return false;
         }
-        /* force CP activities */
-        radeon_ring_force_activity(rdev, ring);
         return radeon_ring_test_lockup(rdev, ring);
 }
 
@@ -2604,8 +2602,6 @@ int r600_cp_resume(struct radeon_device *rdev)
         WREG32(CP_RB_BASE, ring->gpu_addr >> 8);
         WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
 
-        ring->rptr = RREG32(CP_RB_RPTR);
-
         r600_cp_start(rdev);
         ring->ready = true;
         r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring);
@@ -2843,6 +2839,7 @@ int r600_copy_cpdma(struct radeon_device *rdev,
         r = radeon_fence_emit(rdev, fence, ring->idx);
         if (r) {
                 radeon_ring_unlock_undo(rdev, ring);
+                radeon_semaphore_free(rdev, &sem, NULL);
                 return r;
         }
 
@@ -3509,7 +3506,6 @@ int r600_irq_set(struct radeon_device *rdev)
         u32 hpd1, hpd2, hpd3, hpd4 = 0, hpd5 = 0, hpd6 = 0;
         u32 grbm_int_cntl = 0;
         u32 hdmi0, hdmi1;
-        u32 d1grph = 0, d2grph = 0;
         u32 dma_cntl;
         u32 thermal_int = 0;
 
@@ -3618,8 +3614,8 @@ int r600_irq_set(struct radeon_device *rdev)
         WREG32(CP_INT_CNTL, cp_int_cntl);
         WREG32(DMA_CNTL, dma_cntl);
         WREG32(DxMODE_INT_MASK, mode_int);
-        WREG32(D1GRPH_INTERRUPT_CONTROL, d1grph);
-        WREG32(D2GRPH_INTERRUPT_CONTROL, d2grph);
+        WREG32(D1GRPH_INTERRUPT_CONTROL, DxGRPH_PFLIP_INT_MASK);
+        WREG32(D2GRPH_INTERRUPT_CONTROL, DxGRPH_PFLIP_INT_MASK);
         WREG32(GRBM_INT_CNTL, grbm_int_cntl);
         if (ASIC_IS_DCE3(rdev)) {
                 WREG32(DC_HPD1_INT_CONTROL, hpd1);
@@ -3922,6 +3918,14 @@ restart_ih:
                                 break;
                         }
                         break;
+                case 9: /* D1 pflip */
+                        DRM_DEBUG("IH: D1 flip\n");
+                        radeon_crtc_handle_flip(rdev, 0);
+                        break;
+                case 11: /* D2 pflip */
+                        DRM_DEBUG("IH: D2 flip\n");
+                        radeon_crtc_handle_flip(rdev, 1);
+                        break;
                 case 19: /* HPD/DAC hotplug */
                         switch (src_data) {
                         case 0: