aboutsummaryrefslogtreecommitdiffstats
path: root/drivers/gpu/drm/radeon/r600.c
diff options
context:
space:
mode:
Diffstat (limited to 'drivers/gpu/drm/radeon/r600.c')
-rw-r--r--drivers/gpu/drm/radeon/r600.c29
1 files changed, 21 insertions, 8 deletions
diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
index 0f806cc7dc75..9c92db7c896b 100644
--- a/drivers/gpu/drm/radeon/r600.c
+++ b/drivers/gpu/drm/radeon/r600.c
@@ -878,12 +878,15 @@ void r600_pcie_gart_tlb_flush(struct radeon_device *rdev)
878 u32 tmp; 878 u32 tmp;
879 879
880 /* flush hdp cache so updates hit vram */ 880 /* flush hdp cache so updates hit vram */
881 if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740)) { 881 if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) &&
882 !(rdev->flags & RADEON_IS_AGP)) {
882 void __iomem *ptr = (void *)rdev->gart.table.vram.ptr; 883 void __iomem *ptr = (void *)rdev->gart.table.vram.ptr;
883 u32 tmp; 884 u32 tmp;
884 885
885 /* r7xx hw bug. write to HDP_DEBUG1 followed by fb read 886 /* r7xx hw bug. write to HDP_DEBUG1 followed by fb read
886 * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL 887 * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL
888 * This seems to cause problems on some AGP cards. Just use the old
889 * method for them.
887 */ 890 */
888 WREG32(HDP_DEBUG1, 0); 891 WREG32(HDP_DEBUG1, 0);
889 tmp = readl((void __iomem *)ptr); 892 tmp = readl((void __iomem *)ptr);
@@ -1195,8 +1198,10 @@ void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
1195 mc->vram_end, mc->real_vram_size >> 20); 1198 mc->vram_end, mc->real_vram_size >> 20);
1196 } else { 1199 } else {
1197 u64 base = 0; 1200 u64 base = 0;
1198 if (rdev->flags & RADEON_IS_IGP) 1201 if (rdev->flags & RADEON_IS_IGP) {
1199 base = (RREG32(MC_VM_FB_LOCATION) & 0xFFFF) << 24; 1202 base = RREG32(MC_VM_FB_LOCATION) & 0xFFFF;
1203 base <<= 24;
1204 }
1200 radeon_vram_location(rdev, &rdev->mc, base); 1205 radeon_vram_location(rdev, &rdev->mc, base);
1201 rdev->mc.gtt_base_align = 0; 1206 rdev->mc.gtt_base_align = 0;
1202 radeon_gtt_location(rdev, mc); 1207 radeon_gtt_location(rdev, mc);
@@ -1337,13 +1342,19 @@ bool r600_gpu_is_lockup(struct radeon_device *rdev)
1337 u32 srbm_status; 1342 u32 srbm_status;
1338 u32 grbm_status; 1343 u32 grbm_status;
1339 u32 grbm_status2; 1344 u32 grbm_status2;
1345 struct r100_gpu_lockup *lockup;
1340 int r; 1346 int r;
1341 1347
1348 if (rdev->family >= CHIP_RV770)
1349 lockup = &rdev->config.rv770.lockup;
1350 else
1351 lockup = &rdev->config.r600.lockup;
1352
1342 srbm_status = RREG32(R_000E50_SRBM_STATUS); 1353 srbm_status = RREG32(R_000E50_SRBM_STATUS);
1343 grbm_status = RREG32(R_008010_GRBM_STATUS); 1354 grbm_status = RREG32(R_008010_GRBM_STATUS);
1344 grbm_status2 = RREG32(R_008014_GRBM_STATUS2); 1355 grbm_status2 = RREG32(R_008014_GRBM_STATUS2);
1345 if (!G_008010_GUI_ACTIVE(grbm_status)) { 1356 if (!G_008010_GUI_ACTIVE(grbm_status)) {
1346 r100_gpu_lockup_update(&rdev->config.r300.lockup, &rdev->cp); 1357 r100_gpu_lockup_update(lockup, &rdev->cp);
1347 return false; 1358 return false;
1348 } 1359 }
1349 /* force CP activities */ 1360 /* force CP activities */
@@ -1355,7 +1366,7 @@ bool r600_gpu_is_lockup(struct radeon_device *rdev)
1355 radeon_ring_unlock_commit(rdev); 1366 radeon_ring_unlock_commit(rdev);
1356 } 1367 }
1357 rdev->cp.rptr = RREG32(R600_CP_RB_RPTR); 1368 rdev->cp.rptr = RREG32(R600_CP_RB_RPTR);
1358 return r100_gpu_cp_is_lockup(rdev, &rdev->config.r300.lockup, &rdev->cp); 1369 return r100_gpu_cp_is_lockup(rdev, lockup, &rdev->cp);
1359} 1370}
1360 1371
1361int r600_asic_reset(struct radeon_device *rdev) 1372int r600_asic_reset(struct radeon_device *rdev)
@@ -2718,7 +2729,7 @@ static int r600_ih_ring_alloc(struct radeon_device *rdev)
2718 /* Allocate ring buffer */ 2729 /* Allocate ring buffer */
2719 if (rdev->ih.ring_obj == NULL) { 2730 if (rdev->ih.ring_obj == NULL) {
2720 r = radeon_bo_create(rdev, NULL, rdev->ih.ring_size, 2731 r = radeon_bo_create(rdev, NULL, rdev->ih.ring_size,
2721 true, 2732 PAGE_SIZE, true,
2722 RADEON_GEM_DOMAIN_GTT, 2733 RADEON_GEM_DOMAIN_GTT,
2723 &rdev->ih.ring_obj); 2734 &rdev->ih.ring_obj);
2724 if (r) { 2735 if (r) {
@@ -3483,10 +3494,12 @@ int r600_debugfs_mc_info_init(struct radeon_device *rdev)
3483void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo) 3494void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo)
3484{ 3495{
3485 /* r7xx hw bug. write to HDP_DEBUG1 followed by fb read 3496 /* r7xx hw bug. write to HDP_DEBUG1 followed by fb read
3486 * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL 3497 * rather than write to HDP_REG_COHERENCY_FLUSH_CNTL.
3498 * This seems to cause problems on some AGP cards. Just use the old
3499 * method for them.
3487 */ 3500 */
3488 if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) && 3501 if ((rdev->family >= CHIP_RV770) && (rdev->family <= CHIP_RV740) &&
3489 rdev->vram_scratch.ptr) { 3502 rdev->vram_scratch.ptr && !(rdev->flags & RADEON_IS_AGP)) {
3490 void __iomem *ptr = (void *)rdev->vram_scratch.ptr; 3503 void __iomem *ptr = (void *)rdev->vram_scratch.ptr;
3491 u32 tmp; 3504 u32 tmp;
3492 3505