diff options
Diffstat (limited to 'drivers/gpu/drm/radeon/r600.c')
-rw-r--r-- | drivers/gpu/drm/radeon/r600.c | 14 |
1 files changed, 11 insertions, 3 deletions
diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c index 6e887d004eba..bbc189fd3ddc 100644 --- a/drivers/gpu/drm/radeon/r600.c +++ b/drivers/gpu/drm/radeon/r600.c | |||
@@ -2839,6 +2839,7 @@ int r600_copy_cpdma(struct radeon_device *rdev, | |||
2839 | r = radeon_fence_emit(rdev, fence, ring->idx); | 2839 | r = radeon_fence_emit(rdev, fence, ring->idx); |
2840 | if (r) { | 2840 | if (r) { |
2841 | radeon_ring_unlock_undo(rdev, ring); | 2841 | radeon_ring_unlock_undo(rdev, ring); |
2842 | radeon_semaphore_free(rdev, &sem, NULL); | ||
2842 | return r; | 2843 | return r; |
2843 | } | 2844 | } |
2844 | 2845 | ||
@@ -3505,7 +3506,6 @@ int r600_irq_set(struct radeon_device *rdev) | |||
3505 | u32 hpd1, hpd2, hpd3, hpd4 = 0, hpd5 = 0, hpd6 = 0; | 3506 | u32 hpd1, hpd2, hpd3, hpd4 = 0, hpd5 = 0, hpd6 = 0; |
3506 | u32 grbm_int_cntl = 0; | 3507 | u32 grbm_int_cntl = 0; |
3507 | u32 hdmi0, hdmi1; | 3508 | u32 hdmi0, hdmi1; |
3508 | u32 d1grph = 0, d2grph = 0; | ||
3509 | u32 dma_cntl; | 3509 | u32 dma_cntl; |
3510 | u32 thermal_int = 0; | 3510 | u32 thermal_int = 0; |
3511 | 3511 | ||
@@ -3614,8 +3614,8 @@ int r600_irq_set(struct radeon_device *rdev) | |||
3614 | WREG32(CP_INT_CNTL, cp_int_cntl); | 3614 | WREG32(CP_INT_CNTL, cp_int_cntl); |
3615 | WREG32(DMA_CNTL, dma_cntl); | 3615 | WREG32(DMA_CNTL, dma_cntl); |
3616 | WREG32(DxMODE_INT_MASK, mode_int); | 3616 | WREG32(DxMODE_INT_MASK, mode_int); |
3617 | WREG32(D1GRPH_INTERRUPT_CONTROL, d1grph); | 3617 | WREG32(D1GRPH_INTERRUPT_CONTROL, DxGRPH_PFLIP_INT_MASK); |
3618 | WREG32(D2GRPH_INTERRUPT_CONTROL, d2grph); | 3618 | WREG32(D2GRPH_INTERRUPT_CONTROL, DxGRPH_PFLIP_INT_MASK); |
3619 | WREG32(GRBM_INT_CNTL, grbm_int_cntl); | 3619 | WREG32(GRBM_INT_CNTL, grbm_int_cntl); |
3620 | if (ASIC_IS_DCE3(rdev)) { | 3620 | if (ASIC_IS_DCE3(rdev)) { |
3621 | WREG32(DC_HPD1_INT_CONTROL, hpd1); | 3621 | WREG32(DC_HPD1_INT_CONTROL, hpd1); |
@@ -3918,6 +3918,14 @@ restart_ih: | |||
3918 | break; | 3918 | break; |
3919 | } | 3919 | } |
3920 | break; | 3920 | break; |
3921 | case 9: /* D1 pflip */ | ||
3922 | DRM_DEBUG("IH: D1 flip\n"); | ||
3923 | radeon_crtc_handle_flip(rdev, 0); | ||
3924 | break; | ||
3925 | case 11: /* D2 pflip */ | ||
3926 | DRM_DEBUG("IH: D2 flip\n"); | ||
3927 | radeon_crtc_handle_flip(rdev, 1); | ||
3928 | break; | ||
3921 | case 19: /* HPD/DAC hotplug */ | 3929 | case 19: /* HPD/DAC hotplug */ |
3922 | switch (src_data) { | 3930 | switch (src_data) { |
3923 | case 0: | 3931 | case 0: |