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path: root/drivers/gpu/drm/radeon/r600.c
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Diffstat (limited to 'drivers/gpu/drm/radeon/r600.c')
-rw-r--r--drivers/gpu/drm/radeon/r600.c47
1 files changed, 45 insertions, 2 deletions
diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
index c1b0aba4431a..30849eca6e07 100644
--- a/drivers/gpu/drm/radeon/r600.c
+++ b/drivers/gpu/drm/radeon/r600.c
@@ -2504,6 +2504,49 @@ void r600_cp_fini(struct radeon_device *rdev)
2504 * solid fills, and a number of other things. It also 2504 * solid fills, and a number of other things. It also
2505 * has support for tiling/detiling of buffers. 2505 * has support for tiling/detiling of buffers.
2506 */ 2506 */
2507
2508/**
2509 * r600_dma_get_rptr - get the current read pointer
2510 *
2511 * @rdev: radeon_device pointer
2512 * @ring: radeon ring pointer
2513 *
2514 * Get the current rptr from the hardware (r6xx+).
2515 */
2516uint32_t r600_dma_get_rptr(struct radeon_device *rdev,
2517 struct radeon_ring *ring)
2518{
2519 return (radeon_ring_generic_get_rptr(rdev, ring) & 0x3fffc) >> 2;
2520}
2521
2522/**
2523 * r600_dma_get_wptr - get the current write pointer
2524 *
2525 * @rdev: radeon_device pointer
2526 * @ring: radeon ring pointer
2527 *
2528 * Get the current wptr from the hardware (r6xx+).
2529 */
2530uint32_t r600_dma_get_wptr(struct radeon_device *rdev,
2531 struct radeon_ring *ring)
2532{
2533 return (RREG32(ring->wptr_reg) & 0x3fffc) >> 2;
2534}
2535
2536/**
2537 * r600_dma_set_wptr - commit the write pointer
2538 *
2539 * @rdev: radeon_device pointer
2540 * @ring: radeon ring pointer
2541 *
2542 * Write the wptr back to the hardware (r6xx+).
2543 */
2544void r600_dma_set_wptr(struct radeon_device *rdev,
2545 struct radeon_ring *ring)
2546{
2547 WREG32(ring->wptr_reg, (ring->wptr << 2) & 0x3fffc);
2548}
2549
2507/** 2550/**
2508 * r600_dma_stop - stop the async dma engine 2551 * r600_dma_stop - stop the async dma engine
2509 * 2552 *
@@ -3386,14 +3429,14 @@ static int r600_startup(struct radeon_device *rdev)
3386 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]; 3429 ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
3387 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET, 3430 r = radeon_ring_init(rdev, ring, ring->ring_size, RADEON_WB_CP_RPTR_OFFSET,
3388 R600_CP_RB_RPTR, R600_CP_RB_WPTR, 3431 R600_CP_RB_RPTR, R600_CP_RB_WPTR,
3389 0, 0xfffff, RADEON_CP_PACKET2); 3432 RADEON_CP_PACKET2);
3390 if (r) 3433 if (r)
3391 return r; 3434 return r;
3392 3435
3393 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX]; 3436 ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX];
3394 r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET, 3437 r = radeon_ring_init(rdev, ring, ring->ring_size, R600_WB_DMA_RPTR_OFFSET,
3395 DMA_RB_RPTR, DMA_RB_WPTR, 3438 DMA_RB_RPTR, DMA_RB_WPTR,
3396 2, 0x3fffc, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0)); 3439 DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0));
3397 if (r) 3440 if (r)
3398 return r; 3441 return r;
3399 3442