diff options
Diffstat (limited to 'drivers/gpu/drm/radeon/r500_reg.h')
| -rw-r--r-- | drivers/gpu/drm/radeon/r500_reg.h | 100 |
1 files changed, 54 insertions, 46 deletions
diff --git a/drivers/gpu/drm/radeon/r500_reg.h b/drivers/gpu/drm/radeon/r500_reg.h index 74ad89bdf2b5..0cf2ad2a5585 100644 --- a/drivers/gpu/drm/radeon/r500_reg.h +++ b/drivers/gpu/drm/radeon/r500_reg.h | |||
| @@ -717,54 +717,62 @@ | |||
| 717 | #define AVIVO_DVOA_BIT_DEPTH_CONTROL 0x7988 | 717 | #define AVIVO_DVOA_BIT_DEPTH_CONTROL 0x7988 |
| 718 | 718 | ||
| 719 | #define AVIVO_DC_GPIO_HPD_A 0x7e94 | 719 | #define AVIVO_DC_GPIO_HPD_A 0x7e94 |
| 720 | |||
| 721 | #define AVIVO_GPIO_0 0x7e30 | ||
| 722 | #define AVIVO_GPIO_1 0x7e40 | ||
| 723 | #define AVIVO_GPIO_2 0x7e50 | ||
| 724 | #define AVIVO_GPIO_3 0x7e60 | ||
| 725 | |||
| 726 | #define AVIVO_DC_GPIO_HPD_Y 0x7e9c | 720 | #define AVIVO_DC_GPIO_HPD_Y 0x7e9c |
| 727 | 721 | ||
| 728 | #define AVIVO_I2C_STATUS 0x7d30 | 722 | #define AVIVO_DC_I2C_STATUS1 0x7d30 |
| 729 | # define AVIVO_I2C_STATUS_DONE (1 << 0) | 723 | # define AVIVO_DC_I2C_DONE (1 << 0) |
| 730 | # define AVIVO_I2C_STATUS_NACK (1 << 1) | 724 | # define AVIVO_DC_I2C_NACK (1 << 1) |
| 731 | # define AVIVO_I2C_STATUS_HALT (1 << 2) | 725 | # define AVIVO_DC_I2C_HALT (1 << 2) |
| 732 | # define AVIVO_I2C_STATUS_GO (1 << 3) | 726 | # define AVIVO_DC_I2C_GO (1 << 3) |
| 733 | # define AVIVO_I2C_STATUS_MASK 0x7 | 727 | #define AVIVO_DC_I2C_RESET 0x7d34 |
| 734 | /* If radeon_mm_i2c is to be believed, this is HALT, NACK, and maybe | 728 | # define AVIVO_DC_I2C_SOFT_RESET (1 << 0) |
| 735 | * DONE? */ | 729 | # define AVIVO_DC_I2C_ABORT (1 << 8) |
| 736 | # define AVIVO_I2C_STATUS_CMD_RESET 0x7 | 730 | #define AVIVO_DC_I2C_CONTROL1 0x7d38 |
| 737 | # define AVIVO_I2C_STATUS_CMD_WAIT (1 << 3) | 731 | # define AVIVO_DC_I2C_START (1 << 0) |
| 738 | #define AVIVO_I2C_STOP 0x7d34 | 732 | # define AVIVO_DC_I2C_STOP (1 << 1) |
| 739 | #define AVIVO_I2C_START_CNTL 0x7d38 | 733 | # define AVIVO_DC_I2C_RECEIVE (1 << 2) |
| 740 | # define AVIVO_I2C_START (1 << 8) | 734 | # define AVIVO_DC_I2C_EN (1 << 8) |
| 741 | # define AVIVO_I2C_CONNECTOR0 (0 << 16) | 735 | # define AVIVO_DC_I2C_PIN_SELECT(x) ((x) << 16) |
| 742 | # define AVIVO_I2C_CONNECTOR1 (1 << 16) | 736 | # define AVIVO_SEL_DDC1 0 |
| 743 | #define R520_I2C_START (1<<0) | 737 | # define AVIVO_SEL_DDC2 1 |
| 744 | #define R520_I2C_STOP (1<<1) | 738 | # define AVIVO_SEL_DDC3 2 |
| 745 | #define R520_I2C_RX (1<<2) | 739 | #define AVIVO_DC_I2C_CONTROL2 0x7d3c |
| 746 | #define R520_I2C_EN (1<<8) | 740 | # define AVIVO_DC_I2C_ADDR_COUNT(x) ((x) << 0) |
| 747 | #define R520_I2C_DDC1 (0<<16) | 741 | # define AVIVO_DC_I2C_DATA_COUNT(x) ((x) << 8) |
| 748 | #define R520_I2C_DDC2 (1<<16) | 742 | #define AVIVO_DC_I2C_CONTROL3 0x7d40 |
| 749 | #define R520_I2C_DDC3 (2<<16) | 743 | # define AVIVO_DC_I2C_DATA_DRIVE_EN (1 << 0) |
| 750 | #define R520_I2C_DDC_MASK (3<<16) | 744 | # define AVIVO_DC_I2C_DATA_DRIVE_SEL (1 << 1) |
| 751 | #define AVIVO_I2C_CONTROL2 0x7d3c | 745 | # define AVIVO_DC_I2C_CLK_DRIVE_EN (1 << 7) |
| 752 | # define AVIVO_I2C_7D3C_SIZE_SHIFT 8 | 746 | # define AVIVO_DC_I2C_RD_INTRA_BYTE_DELAY(x) ((x) << 8) |
| 753 | # define AVIVO_I2C_7D3C_SIZE_MASK (0xf << 8) | 747 | # define AVIVO_DC_I2C_WR_INTRA_BYTE_DELAY(x) ((x) << 16) |
| 754 | #define AVIVO_I2C_CONTROL3 0x7d40 | 748 | # define AVIVO_DC_I2C_TIME_LIMIT(x) ((x) << 24) |
| 755 | /* Reading is done 4 bytes at a time: read the bottom 8 bits from | 749 | #define AVIVO_DC_I2C_DATA 0x7d44 |
| 756 | * 7d44, four times in a row. | 750 | #define AVIVO_DC_I2C_INTERRUPT_CONTROL 0x7d48 |
| 757 | * Writing is a little more complex. First write DATA with | 751 | # define AVIVO_DC_I2C_INTERRUPT_STATUS (1 << 0) |
| 758 | * 0xnnnnnnzz, then 0xnnnnnnyy, where nnnnnn is some non-deterministic | 752 | # define AVIVO_DC_I2C_INTERRUPT_AK (1 << 8) |
| 759 | * magic number, zz is, I think, the slave address, and yy is the byte | 753 | # define AVIVO_DC_I2C_INTERRUPT_ENABLE (1 << 16) |
| 760 | * you want to write. */ | 754 | #define AVIVO_DC_I2C_ARBITRATION 0x7d50 |
| 761 | #define AVIVO_I2C_DATA 0x7d44 | 755 | # define AVIVO_DC_I2C_SW_WANTS_TO_USE_I2C (1 << 0) |
| 762 | #define R520_I2C_ADDR_COUNT_MASK (0x7) | 756 | # define AVIVO_DC_I2C_SW_CAN_USE_I2C (1 << 1) |
| 763 | #define R520_I2C_DATA_COUNT_SHIFT (8) | 757 | # define AVIVO_DC_I2C_SW_DONE_USING_I2C (1 << 8) |
| 764 | #define R520_I2C_DATA_COUNT_MASK (0xF00) | 758 | # define AVIVO_DC_I2C_HW_NEEDS_I2C (1 << 9) |
| 765 | #define AVIVO_I2C_CNTL 0x7d50 | 759 | # define AVIVO_DC_I2C_ABORT_HDCP_I2C (1 << 16) |
| 766 | # define AVIVO_I2C_EN (1 << 0) | 760 | # define AVIVO_DC_I2C_HW_USING_I2C (1 << 17) |
| 767 | # define AVIVO_I2C_RESET (1 << 8) | 761 | |
| 762 | #define AVIVO_DC_GPIO_DDC1_MASK 0x7e40 | ||
| 763 | #define AVIVO_DC_GPIO_DDC1_A 0x7e44 | ||
| 764 | #define AVIVO_DC_GPIO_DDC1_EN 0x7e48 | ||
| 765 | #define AVIVO_DC_GPIO_DDC1_Y 0x7e4c | ||
| 766 | |||
| 767 | #define AVIVO_DC_GPIO_DDC2_MASK 0x7e50 | ||
| 768 | #define AVIVO_DC_GPIO_DDC2_A 0x7e54 | ||
| 769 | #define AVIVO_DC_GPIO_DDC2_EN 0x7e58 | ||
| 770 | #define AVIVO_DC_GPIO_DDC2_Y 0x7e5c | ||
| 771 | |||
| 772 | #define AVIVO_DC_GPIO_DDC3_MASK 0x7e60 | ||
| 773 | #define AVIVO_DC_GPIO_DDC3_A 0x7e64 | ||
| 774 | #define AVIVO_DC_GPIO_DDC3_EN 0x7e68 | ||
| 775 | #define AVIVO_DC_GPIO_DDC3_Y 0x7e6c | ||
| 768 | 776 | ||
| 769 | #define AVIVO_DISP_INTERRUPT_STATUS 0x7edc | 777 | #define AVIVO_DISP_INTERRUPT_STATUS 0x7edc |
| 770 | # define AVIVO_D1_VBLANK_INTERRUPT (1 << 4) | 778 | # define AVIVO_D1_VBLANK_INTERRUPT (1 << 4) |