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path: root/drivers/gpu/drm/radeon/r420.c
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Diffstat (limited to 'drivers/gpu/drm/radeon/r420.c')
-rw-r--r--drivers/gpu/drm/radeon/r420.c25
1 files changed, 13 insertions, 12 deletions
diff --git a/drivers/gpu/drm/radeon/r420.c b/drivers/gpu/drm/radeon/r420.c
index 1cefdbcc0850..c05a7270cf0c 100644
--- a/drivers/gpu/drm/radeon/r420.c
+++ b/drivers/gpu/drm/radeon/r420.c
@@ -169,6 +169,9 @@ static int r420_startup(struct radeon_device *rdev)
169{ 169{
170 int r; 170 int r;
171 171
172 /* set common regs */
173 r100_set_common_regs(rdev);
174 /* program mc */
172 r300_mc_program(rdev); 175 r300_mc_program(rdev);
173 /* Resume clock */ 176 /* Resume clock */
174 r420_clock_resume(rdev); 177 r420_clock_resume(rdev);
@@ -186,7 +189,6 @@ static int r420_startup(struct radeon_device *rdev)
186 } 189 }
187 r420_pipes_init(rdev); 190 r420_pipes_init(rdev);
188 /* Enable IRQ */ 191 /* Enable IRQ */
189 rdev->irq.sw_int = true;
190 r100_irq_set(rdev); 192 r100_irq_set(rdev);
191 /* 1M ring buffer */ 193 /* 1M ring buffer */
192 r = r100_cp_init(rdev, 1024 * 1024); 194 r = r100_cp_init(rdev, 1024 * 1024);
@@ -229,7 +231,8 @@ int r420_resume(struct radeon_device *rdev)
229 } 231 }
230 /* Resume clock after posting */ 232 /* Resume clock after posting */
231 r420_clock_resume(rdev); 233 r420_clock_resume(rdev);
232 234 /* Initialize surface registers */
235 radeon_surface_init(rdev);
233 return r420_startup(rdev); 236 return r420_startup(rdev);
234} 237}
235 238
@@ -258,7 +261,7 @@ void r420_fini(struct radeon_device *rdev)
258 radeon_agp_fini(rdev); 261 radeon_agp_fini(rdev);
259 radeon_irq_kms_fini(rdev); 262 radeon_irq_kms_fini(rdev);
260 radeon_fence_driver_fini(rdev); 263 radeon_fence_driver_fini(rdev);
261 radeon_object_fini(rdev); 264 radeon_bo_fini(rdev);
262 if (rdev->is_atom_bios) { 265 if (rdev->is_atom_bios) {
263 radeon_atombios_fini(rdev); 266 radeon_atombios_fini(rdev);
264 } else { 267 } else {
@@ -301,14 +304,9 @@ int r420_init(struct radeon_device *rdev)
301 RREG32(R_0007C0_CP_STAT)); 304 RREG32(R_0007C0_CP_STAT));
302 } 305 }
303 /* check if cards are posted or not */ 306 /* check if cards are posted or not */
304 if (!radeon_card_posted(rdev) && rdev->bios) { 307 if (radeon_boot_test_post_card(rdev) == false)
305 DRM_INFO("GPU not posted. posting now...\n"); 308 return -EINVAL;
306 if (rdev->is_atom_bios) { 309
307 atom_asic_init(rdev->mode_info.atom_context);
308 } else {
309 radeon_combios_asic_init(rdev->ddev);
310 }
311 }
312 /* Initialize clocks */ 310 /* Initialize clocks */
313 radeon_get_clock_info(rdev->ddev); 311 radeon_get_clock_info(rdev->ddev);
314 /* Initialize power management */ 312 /* Initialize power management */
@@ -331,10 +329,13 @@ int r420_init(struct radeon_device *rdev)
331 return r; 329 return r;
332 } 330 }
333 /* Memory manager */ 331 /* Memory manager */
334 r = radeon_object_init(rdev); 332 r = radeon_bo_init(rdev);
335 if (r) { 333 if (r) {
336 return r; 334 return r;
337 } 335 }
336 if (rdev->family == CHIP_R420)
337 r100_enable_bm(rdev);
338
338 if (rdev->flags & RADEON_IS_PCIE) { 339 if (rdev->flags & RADEON_IS_PCIE) {
339 r = rv370_pcie_gart_init(rdev); 340 r = rv370_pcie_gart_init(rdev);
340 if (r) 341 if (r)