diff options
Diffstat (limited to 'drivers/gpu/drm/radeon/r300.c')
-rw-r--r-- | drivers/gpu/drm/radeon/r300.c | 16 |
1 files changed, 15 insertions, 1 deletions
diff --git a/drivers/gpu/drm/radeon/r300.c b/drivers/gpu/drm/radeon/r300.c index 1ebea8cc8c93..e491d40d4d54 100644 --- a/drivers/gpu/drm/radeon/r300.c +++ b/drivers/gpu/drm/radeon/r300.c | |||
@@ -33,6 +33,7 @@ | |||
33 | #include "radeon_drm.h" | 33 | #include "radeon_drm.h" |
34 | #include "r100_track.h" | 34 | #include "r100_track.h" |
35 | #include "r300d.h" | 35 | #include "r300d.h" |
36 | #include "rv350d.h" | ||
36 | 37 | ||
37 | #include "r300_reg_safe.h" | 38 | #include "r300_reg_safe.h" |
38 | 39 | ||
@@ -63,7 +64,6 @@ int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p, | |||
63 | * Some of these functions might be used by newer ASICs. | 64 | * Some of these functions might be used by newer ASICs. |
64 | */ | 65 | */ |
65 | void r300_gpu_init(struct radeon_device *rdev); | 66 | void r300_gpu_init(struct radeon_device *rdev); |
66 | int r300_mc_wait_for_idle(struct radeon_device *rdev); | ||
67 | int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev); | 67 | int rv370_debugfs_pcie_gart_info_init(struct radeon_device *rdev); |
68 | 68 | ||
69 | 69 | ||
@@ -1265,3 +1265,17 @@ void r300_mc_program(struct radeon_device *rdev) | |||
1265 | S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16)); | 1265 | S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16)); |
1266 | r100_mc_resume(rdev, &save); | 1266 | r100_mc_resume(rdev, &save); |
1267 | } | 1267 | } |
1268 | |||
1269 | void r300_clock_startup(struct radeon_device *rdev) | ||
1270 | { | ||
1271 | u32 tmp; | ||
1272 | |||
1273 | if (radeon_dynclks != -1 && radeon_dynclks) | ||
1274 | radeon_legacy_set_clock_gating(rdev, 1); | ||
1275 | /* We need to force on some of the block */ | ||
1276 | tmp = RREG32_PLL(R_00000D_SCLK_CNTL); | ||
1277 | tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1); | ||
1278 | if ((rdev->family == CHIP_RV350) || (rdev->family == CHIP_RV380)) | ||
1279 | tmp |= S_00000D_FORCE_VAP(1); | ||
1280 | WREG32_PLL(R_00000D_SCLK_CNTL, tmp); | ||
1281 | } | ||