diff options
Diffstat (limited to 'drivers/gpu/drm/radeon/r100d.h')
| -rw-r--r-- | drivers/gpu/drm/radeon/r100d.h | 38 |
1 files changed, 19 insertions, 19 deletions
diff --git a/drivers/gpu/drm/radeon/r100d.h b/drivers/gpu/drm/radeon/r100d.h index c4b257ec920e..1595a5d132df 100644 --- a/drivers/gpu/drm/radeon/r100d.h +++ b/drivers/gpu/drm/radeon/r100d.h | |||
| @@ -403,25 +403,25 @@ | |||
| 403 | #define S_000360_CUR2_LOCK(x) (((x) & 0x1) << 31) | 403 | #define S_000360_CUR2_LOCK(x) (((x) & 0x1) << 31) |
| 404 | #define G_000360_CUR2_LOCK(x) (((x) >> 31) & 0x1) | 404 | #define G_000360_CUR2_LOCK(x) (((x) >> 31) & 0x1) |
| 405 | #define C_000360_CUR2_LOCK 0x7FFFFFFF | 405 | #define C_000360_CUR2_LOCK 0x7FFFFFFF |
| 406 | #define R_0003C0_GENMO_WT 0x0003C0 | 406 | #define R_0003C2_GENMO_WT 0x0003C0 |
| 407 | #define S_0003C0_GENMO_MONO_ADDRESS_B(x) (((x) & 0x1) << 0) | 407 | #define S_0003C2_GENMO_MONO_ADDRESS_B(x) (((x) & 0x1) << 0) |
| 408 | #define G_0003C0_GENMO_MONO_ADDRESS_B(x) (((x) >> 0) & 0x1) | 408 | #define G_0003C2_GENMO_MONO_ADDRESS_B(x) (((x) >> 0) & 0x1) |
| 409 | #define C_0003C0_GENMO_MONO_ADDRESS_B 0xFFFFFFFE | 409 | #define C_0003C2_GENMO_MONO_ADDRESS_B 0xFE |
| 410 | #define S_0003C0_VGA_RAM_EN(x) (((x) & 0x1) << 1) | 410 | #define S_0003C2_VGA_RAM_EN(x) (((x) & 0x1) << 1) |
| 411 | #define G_0003C0_VGA_RAM_EN(x) (((x) >> 1) & 0x1) | 411 | #define G_0003C2_VGA_RAM_EN(x) (((x) >> 1) & 0x1) |
| 412 | #define C_0003C0_VGA_RAM_EN 0xFFFFFFFD | 412 | #define C_0003C2_VGA_RAM_EN 0xFD |
| 413 | #define S_0003C0_VGA_CKSEL(x) (((x) & 0x3) << 2) | 413 | #define S_0003C2_VGA_CKSEL(x) (((x) & 0x3) << 2) |
| 414 | #define G_0003C0_VGA_CKSEL(x) (((x) >> 2) & 0x3) | 414 | #define G_0003C2_VGA_CKSEL(x) (((x) >> 2) & 0x3) |
| 415 | #define C_0003C0_VGA_CKSEL 0xFFFFFFF3 | 415 | #define C_0003C2_VGA_CKSEL 0xF3 |
| 416 | #define S_0003C0_ODD_EVEN_MD_PGSEL(x) (((x) & 0x1) << 5) | 416 | #define S_0003C2_ODD_EVEN_MD_PGSEL(x) (((x) & 0x1) << 5) |
| 417 | #define G_0003C0_ODD_EVEN_MD_PGSEL(x) (((x) >> 5) & 0x1) | 417 | #define G_0003C2_ODD_EVEN_MD_PGSEL(x) (((x) >> 5) & 0x1) |
| 418 | #define C_0003C0_ODD_EVEN_MD_PGSEL 0xFFFFFFDF | 418 | #define C_0003C2_ODD_EVEN_MD_PGSEL 0xDF |
| 419 | #define S_0003C0_VGA_HSYNC_POL(x) (((x) & 0x1) << 6) | 419 | #define S_0003C2_VGA_HSYNC_POL(x) (((x) & 0x1) << 6) |
| 420 | #define G_0003C0_VGA_HSYNC_POL(x) (((x) >> 6) & 0x1) | 420 | #define G_0003C2_VGA_HSYNC_POL(x) (((x) >> 6) & 0x1) |
| 421 | #define C_0003C0_VGA_HSYNC_POL 0xFFFFFFBF | 421 | #define C_0003C2_VGA_HSYNC_POL 0xBF |
| 422 | #define S_0003C0_VGA_VSYNC_POL(x) (((x) & 0x1) << 7) | 422 | #define S_0003C2_VGA_VSYNC_POL(x) (((x) & 0x1) << 7) |
| 423 | #define G_0003C0_VGA_VSYNC_POL(x) (((x) >> 7) & 0x1) | 423 | #define G_0003C2_VGA_VSYNC_POL(x) (((x) >> 7) & 0x1) |
| 424 | #define C_0003C0_VGA_VSYNC_POL 0xFFFFFF7F | 424 | #define C_0003C2_VGA_VSYNC_POL 0x7F |
| 425 | #define R_0003F8_CRTC2_GEN_CNTL 0x0003F8 | 425 | #define R_0003F8_CRTC2_GEN_CNTL 0x0003F8 |
| 426 | #define S_0003F8_CRTC2_DBL_SCAN_EN(x) (((x) & 0x1) << 0) | 426 | #define S_0003F8_CRTC2_DBL_SCAN_EN(x) (((x) & 0x1) << 0) |
| 427 | #define G_0003F8_CRTC2_DBL_SCAN_EN(x) (((x) >> 0) & 0x1) | 427 | #define G_0003F8_CRTC2_DBL_SCAN_EN(x) (((x) >> 0) & 0x1) |