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path: root/drivers/gpu/drm/radeon/r100.c
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Diffstat (limited to 'drivers/gpu/drm/radeon/r100.c')
-rw-r--r--drivers/gpu/drm/radeon/r100.c25
1 files changed, 19 insertions, 6 deletions
diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c
index a6e6f179b1d2..c9580497ede4 100644
--- a/drivers/gpu/drm/radeon/r100.c
+++ b/drivers/gpu/drm/radeon/r100.c
@@ -32,6 +32,7 @@
32#include "radeon_drm.h" 32#include "radeon_drm.h"
33#include "radeon_reg.h" 33#include "radeon_reg.h"
34#include "radeon.h" 34#include "radeon.h"
35#include "radeon_asic.h"
35#include "r100d.h" 36#include "r100d.h"
36#include "rs100d.h" 37#include "rs100d.h"
37#include "rv200d.h" 38#include "rv200d.h"
@@ -236,9 +237,9 @@ int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
236 237
237void r100_pci_gart_fini(struct radeon_device *rdev) 238void r100_pci_gart_fini(struct radeon_device *rdev)
238{ 239{
240 radeon_gart_fini(rdev);
239 r100_pci_gart_disable(rdev); 241 r100_pci_gart_disable(rdev);
240 radeon_gart_table_ram_free(rdev); 242 radeon_gart_table_ram_free(rdev);
241 radeon_gart_fini(rdev);
242} 243}
243 244
244int r100_irq_set(struct radeon_device *rdev) 245int r100_irq_set(struct radeon_device *rdev)
@@ -313,10 +314,12 @@ int r100_irq_process(struct radeon_device *rdev)
313 /* Vertical blank interrupts */ 314 /* Vertical blank interrupts */
314 if (status & RADEON_CRTC_VBLANK_STAT) { 315 if (status & RADEON_CRTC_VBLANK_STAT) {
315 drm_handle_vblank(rdev->ddev, 0); 316 drm_handle_vblank(rdev->ddev, 0);
317 rdev->pm.vblank_sync = true;
316 wake_up(&rdev->irq.vblank_queue); 318 wake_up(&rdev->irq.vblank_queue);
317 } 319 }
318 if (status & RADEON_CRTC2_VBLANK_STAT) { 320 if (status & RADEON_CRTC2_VBLANK_STAT) {
319 drm_handle_vblank(rdev->ddev, 1); 321 drm_handle_vblank(rdev->ddev, 1);
322 rdev->pm.vblank_sync = true;
320 wake_up(&rdev->irq.vblank_queue); 323 wake_up(&rdev->irq.vblank_queue);
321 } 324 }
322 if (status & RADEON_FP_DETECT_STAT) { 325 if (status & RADEON_FP_DETECT_STAT) {
@@ -742,6 +745,8 @@ int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
742 udelay(10); 745 udelay(10);
743 rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR); 746 rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR);
744 rdev->cp.wptr = RREG32(RADEON_CP_RB_WPTR); 747 rdev->cp.wptr = RREG32(RADEON_CP_RB_WPTR);
748 /* protect against crazy HW on resume */
749 rdev->cp.wptr &= rdev->cp.ptr_mask;
745 /* Set cp mode to bus mastering & enable cp*/ 750 /* Set cp mode to bus mastering & enable cp*/
746 WREG32(RADEON_CP_CSQ_MODE, 751 WREG32(RADEON_CP_CSQ_MODE,
747 REG_SET(RADEON_INDIRECT2_START, indirect2_start) | 752 REG_SET(RADEON_INDIRECT2_START, indirect2_start) |
@@ -1805,6 +1810,7 @@ void r100_set_common_regs(struct radeon_device *rdev)
1805{ 1810{
1806 struct drm_device *dev = rdev->ddev; 1811 struct drm_device *dev = rdev->ddev;
1807 bool force_dac2 = false; 1812 bool force_dac2 = false;
1813 u32 tmp;
1808 1814
1809 /* set these so they don't interfere with anything */ 1815 /* set these so they don't interfere with anything */
1810 WREG32(RADEON_OV0_SCALE_CNTL, 0); 1816 WREG32(RADEON_OV0_SCALE_CNTL, 0);
@@ -1876,6 +1882,12 @@ void r100_set_common_regs(struct radeon_device *rdev)
1876 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug); 1882 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
1877 WREG32(RADEON_DAC_CNTL2, dac2_cntl); 1883 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
1878 } 1884 }
1885
1886 /* switch PM block to ACPI mode */
1887 tmp = RREG32_PLL(RADEON_PLL_PWRMGT_CNTL);
1888 tmp &= ~RADEON_PM_MODE_SEL;
1889 WREG32_PLL(RADEON_PLL_PWRMGT_CNTL, tmp);
1890
1879} 1891}
1880 1892
1881/* 1893/*
@@ -2023,6 +2035,7 @@ void r100_mc_init(struct radeon_device *rdev)
2023 radeon_vram_location(rdev, &rdev->mc, base); 2035 radeon_vram_location(rdev, &rdev->mc, base);
2024 if (!(rdev->flags & RADEON_IS_AGP)) 2036 if (!(rdev->flags & RADEON_IS_AGP))
2025 radeon_gtt_location(rdev, &rdev->mc); 2037 radeon_gtt_location(rdev, &rdev->mc);
2038 radeon_update_bandwidth_info(rdev);
2026} 2039}
2027 2040
2028 2041
@@ -2386,6 +2399,8 @@ void r100_bandwidth_update(struct radeon_device *rdev)
2386 uint32_t pixel_bytes1 = 0; 2399 uint32_t pixel_bytes1 = 0;
2387 uint32_t pixel_bytes2 = 0; 2400 uint32_t pixel_bytes2 = 0;
2388 2401
2402 radeon_update_display_priority(rdev);
2403
2389 if (rdev->mode_info.crtcs[0]->base.enabled) { 2404 if (rdev->mode_info.crtcs[0]->base.enabled) {
2390 mode1 = &rdev->mode_info.crtcs[0]->base.mode; 2405 mode1 = &rdev->mode_info.crtcs[0]->base.mode;
2391 pixel_bytes1 = rdev->mode_info.crtcs[0]->base.fb->bits_per_pixel / 8; 2406 pixel_bytes1 = rdev->mode_info.crtcs[0]->base.fb->bits_per_pixel / 8;
@@ -2414,11 +2429,8 @@ void r100_bandwidth_update(struct radeon_device *rdev)
2414 /* 2429 /*
2415 * determine is there is enough bw for current mode 2430 * determine is there is enough bw for current mode
2416 */ 2431 */
2417 mclk_ff.full = rfixed_const(rdev->clock.default_mclk); 2432 sclk_ff = rdev->pm.sclk;
2418 temp_ff.full = rfixed_const(100); 2433 mclk_ff = rdev->pm.mclk;
2419 mclk_ff.full = rfixed_div(mclk_ff, temp_ff);
2420 sclk_ff.full = rfixed_const(rdev->clock.default_sclk);
2421 sclk_ff.full = rfixed_div(sclk_ff, temp_ff);
2422 2434
2423 temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1); 2435 temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1);
2424 temp_ff.full = rfixed_const(temp); 2436 temp_ff.full = rfixed_const(temp);
@@ -3441,6 +3453,7 @@ int r100_suspend(struct radeon_device *rdev)
3441 3453
3442void r100_fini(struct radeon_device *rdev) 3454void r100_fini(struct radeon_device *rdev)
3443{ 3455{
3456 radeon_pm_fini(rdev);
3444 r100_cp_fini(rdev); 3457 r100_cp_fini(rdev);
3445 r100_wb_fini(rdev); 3458 r100_wb_fini(rdev);
3446 r100_ib_fini(rdev); 3459 r100_ib_fini(rdev);