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path: root/drivers/gpu/drm/radeon/r100.c
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Diffstat (limited to 'drivers/gpu/drm/radeon/r100.c')
-rw-r--r--drivers/gpu/drm/radeon/r100.c40
1 files changed, 20 insertions, 20 deletions
diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c
index 1690a2dc0721..0a894aee7406 100644
--- a/drivers/gpu/drm/radeon/r100.c
+++ b/drivers/gpu/drm/radeon/r100.c
@@ -1274,12 +1274,12 @@ int r100_reloc_pitch_offset(struct radeon_cs_parser *p,
1274 1274
1275 value = radeon_get_ib_value(p, idx); 1275 value = radeon_get_ib_value(p, idx);
1276 tmp = value & 0x003fffff; 1276 tmp = value & 0x003fffff;
1277 tmp += (((u32)reloc->lobj.gpu_offset) >> 10); 1277 tmp += (((u32)reloc->gpu_offset) >> 10);
1278 1278
1279 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { 1279 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
1280 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) 1280 if (reloc->tiling_flags & RADEON_TILING_MACRO)
1281 tile_flags |= RADEON_DST_TILE_MACRO; 1281 tile_flags |= RADEON_DST_TILE_MACRO;
1282 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) { 1282 if (reloc->tiling_flags & RADEON_TILING_MICRO) {
1283 if (reg == RADEON_SRC_PITCH_OFFSET) { 1283 if (reg == RADEON_SRC_PITCH_OFFSET) {
1284 DRM_ERROR("Cannot src blit from microtiled surface\n"); 1284 DRM_ERROR("Cannot src blit from microtiled surface\n");
1285 radeon_cs_dump_packet(p, pkt); 1285 radeon_cs_dump_packet(p, pkt);
@@ -1325,7 +1325,7 @@ int r100_packet3_load_vbpntr(struct radeon_cs_parser *p,
1325 return r; 1325 return r;
1326 } 1326 }
1327 idx_value = radeon_get_ib_value(p, idx); 1327 idx_value = radeon_get_ib_value(p, idx);
1328 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset); 1328 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->gpu_offset);
1329 1329
1330 track->arrays[i + 0].esize = idx_value >> 8; 1330 track->arrays[i + 0].esize = idx_value >> 8;
1331 track->arrays[i + 0].robj = reloc->robj; 1331 track->arrays[i + 0].robj = reloc->robj;
@@ -1337,7 +1337,7 @@ int r100_packet3_load_vbpntr(struct radeon_cs_parser *p,
1337 radeon_cs_dump_packet(p, pkt); 1337 radeon_cs_dump_packet(p, pkt);
1338 return r; 1338 return r;
1339 } 1339 }
1340 ib[idx+2] = radeon_get_ib_value(p, idx + 2) + ((u32)reloc->lobj.gpu_offset); 1340 ib[idx+2] = radeon_get_ib_value(p, idx + 2) + ((u32)reloc->gpu_offset);
1341 track->arrays[i + 1].robj = reloc->robj; 1341 track->arrays[i + 1].robj = reloc->robj;
1342 track->arrays[i + 1].esize = idx_value >> 24; 1342 track->arrays[i + 1].esize = idx_value >> 24;
1343 track->arrays[i + 1].esize &= 0x7F; 1343 track->arrays[i + 1].esize &= 0x7F;
@@ -1351,7 +1351,7 @@ int r100_packet3_load_vbpntr(struct radeon_cs_parser *p,
1351 return r; 1351 return r;
1352 } 1352 }
1353 idx_value = radeon_get_ib_value(p, idx); 1353 idx_value = radeon_get_ib_value(p, idx);
1354 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->lobj.gpu_offset); 1354 ib[idx+1] = radeon_get_ib_value(p, idx + 1) + ((u32)reloc->gpu_offset);
1355 track->arrays[i + 0].robj = reloc->robj; 1355 track->arrays[i + 0].robj = reloc->robj;
1356 track->arrays[i + 0].esize = idx_value >> 8; 1356 track->arrays[i + 0].esize = idx_value >> 8;
1357 track->arrays[i + 0].esize &= 0x7F; 1357 track->arrays[i + 0].esize &= 0x7F;
@@ -1594,7 +1594,7 @@ static int r100_packet0_check(struct radeon_cs_parser *p,
1594 track->zb.robj = reloc->robj; 1594 track->zb.robj = reloc->robj;
1595 track->zb.offset = idx_value; 1595 track->zb.offset = idx_value;
1596 track->zb_dirty = true; 1596 track->zb_dirty = true;
1597 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); 1597 ib[idx] = idx_value + ((u32)reloc->gpu_offset);
1598 break; 1598 break;
1599 case RADEON_RB3D_COLOROFFSET: 1599 case RADEON_RB3D_COLOROFFSET:
1600 r = radeon_cs_packet_next_reloc(p, &reloc, 0); 1600 r = radeon_cs_packet_next_reloc(p, &reloc, 0);
@@ -1607,7 +1607,7 @@ static int r100_packet0_check(struct radeon_cs_parser *p,
1607 track->cb[0].robj = reloc->robj; 1607 track->cb[0].robj = reloc->robj;
1608 track->cb[0].offset = idx_value; 1608 track->cb[0].offset = idx_value;
1609 track->cb_dirty = true; 1609 track->cb_dirty = true;
1610 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); 1610 ib[idx] = idx_value + ((u32)reloc->gpu_offset);
1611 break; 1611 break;
1612 case RADEON_PP_TXOFFSET_0: 1612 case RADEON_PP_TXOFFSET_0:
1613 case RADEON_PP_TXOFFSET_1: 1613 case RADEON_PP_TXOFFSET_1:
@@ -1621,16 +1621,16 @@ static int r100_packet0_check(struct radeon_cs_parser *p,
1621 return r; 1621 return r;
1622 } 1622 }
1623 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { 1623 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
1624 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) 1624 if (reloc->tiling_flags & RADEON_TILING_MACRO)
1625 tile_flags |= RADEON_TXO_MACRO_TILE; 1625 tile_flags |= RADEON_TXO_MACRO_TILE;
1626 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) 1626 if (reloc->tiling_flags & RADEON_TILING_MICRO)
1627 tile_flags |= RADEON_TXO_MICRO_TILE_X2; 1627 tile_flags |= RADEON_TXO_MICRO_TILE_X2;
1628 1628
1629 tmp = idx_value & ~(0x7 << 2); 1629 tmp = idx_value & ~(0x7 << 2);
1630 tmp |= tile_flags; 1630 tmp |= tile_flags;
1631 ib[idx] = tmp + ((u32)reloc->lobj.gpu_offset); 1631 ib[idx] = tmp + ((u32)reloc->gpu_offset);
1632 } else 1632 } else
1633 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); 1633 ib[idx] = idx_value + ((u32)reloc->gpu_offset);
1634 track->textures[i].robj = reloc->robj; 1634 track->textures[i].robj = reloc->robj;
1635 track->tex_dirty = true; 1635 track->tex_dirty = true;
1636 break; 1636 break;
@@ -1648,7 +1648,7 @@ static int r100_packet0_check(struct radeon_cs_parser *p,
1648 return r; 1648 return r;
1649 } 1649 }
1650 track->textures[0].cube_info[i].offset = idx_value; 1650 track->textures[0].cube_info[i].offset = idx_value;
1651 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); 1651 ib[idx] = idx_value + ((u32)reloc->gpu_offset);
1652 track->textures[0].cube_info[i].robj = reloc->robj; 1652 track->textures[0].cube_info[i].robj = reloc->robj;
1653 track->tex_dirty = true; 1653 track->tex_dirty = true;
1654 break; 1654 break;
@@ -1666,7 +1666,7 @@ static int r100_packet0_check(struct radeon_cs_parser *p,
1666 return r; 1666 return r;
1667 } 1667 }
1668 track->textures[1].cube_info[i].offset = idx_value; 1668 track->textures[1].cube_info[i].offset = idx_value;
1669 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); 1669 ib[idx] = idx_value + ((u32)reloc->gpu_offset);
1670 track->textures[1].cube_info[i].robj = reloc->robj; 1670 track->textures[1].cube_info[i].robj = reloc->robj;
1671 track->tex_dirty = true; 1671 track->tex_dirty = true;
1672 break; 1672 break;
@@ -1684,7 +1684,7 @@ static int r100_packet0_check(struct radeon_cs_parser *p,
1684 return r; 1684 return r;
1685 } 1685 }
1686 track->textures[2].cube_info[i].offset = idx_value; 1686 track->textures[2].cube_info[i].offset = idx_value;
1687 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); 1687 ib[idx] = idx_value + ((u32)reloc->gpu_offset);
1688 track->textures[2].cube_info[i].robj = reloc->robj; 1688 track->textures[2].cube_info[i].robj = reloc->robj;
1689 track->tex_dirty = true; 1689 track->tex_dirty = true;
1690 break; 1690 break;
@@ -1702,9 +1702,9 @@ static int r100_packet0_check(struct radeon_cs_parser *p,
1702 return r; 1702 return r;
1703 } 1703 }
1704 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) { 1704 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
1705 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO) 1705 if (reloc->tiling_flags & RADEON_TILING_MACRO)
1706 tile_flags |= RADEON_COLOR_TILE_ENABLE; 1706 tile_flags |= RADEON_COLOR_TILE_ENABLE;
1707 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO) 1707 if (reloc->tiling_flags & RADEON_TILING_MICRO)
1708 tile_flags |= RADEON_COLOR_MICROTILE_ENABLE; 1708 tile_flags |= RADEON_COLOR_MICROTILE_ENABLE;
1709 1709
1710 tmp = idx_value & ~(0x7 << 16); 1710 tmp = idx_value & ~(0x7 << 16);
@@ -1772,7 +1772,7 @@ static int r100_packet0_check(struct radeon_cs_parser *p,
1772 radeon_cs_dump_packet(p, pkt); 1772 radeon_cs_dump_packet(p, pkt);
1773 return r; 1773 return r;
1774 } 1774 }
1775 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset); 1775 ib[idx] = idx_value + ((u32)reloc->gpu_offset);
1776 break; 1776 break;
1777 case RADEON_PP_CNTL: 1777 case RADEON_PP_CNTL:
1778 { 1778 {
@@ -1932,7 +1932,7 @@ static int r100_packet3_check(struct radeon_cs_parser *p,
1932 radeon_cs_dump_packet(p, pkt); 1932 radeon_cs_dump_packet(p, pkt);
1933 return r; 1933 return r;
1934 } 1934 }
1935 ib[idx+1] = radeon_get_ib_value(p, idx+1) + ((u32)reloc->lobj.gpu_offset); 1935 ib[idx+1] = radeon_get_ib_value(p, idx+1) + ((u32)reloc->gpu_offset);
1936 r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj); 1936 r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);
1937 if (r) { 1937 if (r) {
1938 return r; 1938 return r;
@@ -1946,7 +1946,7 @@ static int r100_packet3_check(struct radeon_cs_parser *p,
1946 radeon_cs_dump_packet(p, pkt); 1946 radeon_cs_dump_packet(p, pkt);
1947 return r; 1947 return r;
1948 } 1948 }
1949 ib[idx] = radeon_get_ib_value(p, idx) + ((u32)reloc->lobj.gpu_offset); 1949 ib[idx] = radeon_get_ib_value(p, idx) + ((u32)reloc->gpu_offset);
1950 track->num_arrays = 1; 1950 track->num_arrays = 1;
1951 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 2)); 1951 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 2));
1952 1952
generated by cgit v1.2.2 (git 2.25.0) at 2025-03-04 01:47:43 -0500