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path: root/drivers/gpu/drm/radeon/r100.c
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Diffstat (limited to 'drivers/gpu/drm/radeon/r100.c')
-rw-r--r--drivers/gpu/drm/radeon/r100.c14
1 files changed, 11 insertions, 3 deletions
diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c
index d2099146fc40..dc45ec1d4189 100644
--- a/drivers/gpu/drm/radeon/r100.c
+++ b/drivers/gpu/drm/radeon/r100.c
@@ -3100,7 +3100,7 @@ void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save)
3100 WREG32(R_000740_CP_CSQ_CNTL, 0); 3100 WREG32(R_000740_CP_CSQ_CNTL, 0);
3101 3101
3102 /* Save few CRTC registers */ 3102 /* Save few CRTC registers */
3103 save->GENMO_WT = RREG32(R_0003C0_GENMO_WT); 3103 save->GENMO_WT = RREG8(R_0003C2_GENMO_WT);
3104 save->CRTC_EXT_CNTL = RREG32(R_000054_CRTC_EXT_CNTL); 3104 save->CRTC_EXT_CNTL = RREG32(R_000054_CRTC_EXT_CNTL);
3105 save->CRTC_GEN_CNTL = RREG32(R_000050_CRTC_GEN_CNTL); 3105 save->CRTC_GEN_CNTL = RREG32(R_000050_CRTC_GEN_CNTL);
3106 save->CUR_OFFSET = RREG32(R_000260_CUR_OFFSET); 3106 save->CUR_OFFSET = RREG32(R_000260_CUR_OFFSET);
@@ -3110,7 +3110,7 @@ void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save)
3110 } 3110 }
3111 3111
3112 /* Disable VGA aperture access */ 3112 /* Disable VGA aperture access */
3113 WREG32(R_0003C0_GENMO_WT, C_0003C0_VGA_RAM_EN & save->GENMO_WT); 3113 WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & save->GENMO_WT);
3114 /* Disable cursor, overlay, crtc */ 3114 /* Disable cursor, overlay, crtc */
3115 WREG32(R_000260_CUR_OFFSET, save->CUR_OFFSET | S_000260_CUR_LOCK(1)); 3115 WREG32(R_000260_CUR_OFFSET, save->CUR_OFFSET | S_000260_CUR_LOCK(1));
3116 WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL | 3116 WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL |
@@ -3142,10 +3142,18 @@ void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save)
3142 rdev->mc.vram_location); 3142 rdev->mc.vram_location);
3143 } 3143 }
3144 /* Restore CRTC registers */ 3144 /* Restore CRTC registers */
3145 WREG32(R_0003C0_GENMO_WT, save->GENMO_WT); 3145 WREG8(R_0003C2_GENMO_WT, save->GENMO_WT);
3146 WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL); 3146 WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL);
3147 WREG32(R_000050_CRTC_GEN_CNTL, save->CRTC_GEN_CNTL); 3147 WREG32(R_000050_CRTC_GEN_CNTL, save->CRTC_GEN_CNTL);
3148 if (!(rdev->flags & RADEON_SINGLE_CRTC)) { 3148 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3149 WREG32(R_0003F8_CRTC2_GEN_CNTL, save->CRTC2_GEN_CNTL); 3149 WREG32(R_0003F8_CRTC2_GEN_CNTL, save->CRTC2_GEN_CNTL);
3150 } 3150 }
3151} 3151}
3152
3153void r100_vga_render_disable(struct radeon_device *rdev)
3154{
3155 u32 tmp;
3156
3157 tmp = RREG8(R_0003C2_GENMO_WT);
3158 WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & tmp);
3159}