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path: root/drivers/gpu/drm/radeon/ni.c
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Diffstat (limited to 'drivers/gpu/drm/radeon/ni.c')
-rw-r--r--drivers/gpu/drm/radeon/ni.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/gpu/drm/radeon/ni.c b/drivers/gpu/drm/radeon/ni.c
index 56bd4f3be4fe..5b6e47765656 100644
--- a/drivers/gpu/drm/radeon/ni.c
+++ b/drivers/gpu/drm/radeon/ni.c
@@ -1560,8 +1560,8 @@ static int cayman_cp_resume(struct radeon_device *rdev)
1560 1560
1561 /* Set ring buffer size */ 1561 /* Set ring buffer size */
1562 ring = &rdev->ring[ridx[i]]; 1562 ring = &rdev->ring[ridx[i]];
1563 rb_cntl = drm_order(ring->ring_size / 8); 1563 rb_cntl = order_base_2(ring->ring_size / 8);
1564 rb_cntl |= drm_order(RADEON_GPU_PAGE_SIZE/8) << 8; 1564 rb_cntl |= order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8;
1565#ifdef __BIG_ENDIAN 1565#ifdef __BIG_ENDIAN
1566 rb_cntl |= BUF_SWAP_32BIT; 1566 rb_cntl |= BUF_SWAP_32BIT;
1567#endif 1567#endif
@@ -1720,7 +1720,7 @@ int cayman_dma_resume(struct radeon_device *rdev)
1720 WREG32(DMA_SEM_WAIT_FAIL_TIMER_CNTL + reg_offset, 0); 1720 WREG32(DMA_SEM_WAIT_FAIL_TIMER_CNTL + reg_offset, 0);
1721 1721
1722 /* Set ring buffer size in dwords */ 1722 /* Set ring buffer size in dwords */
1723 rb_bufsz = drm_order(ring->ring_size / 4); 1723 rb_bufsz = order_base_2(ring->ring_size / 4);
1724 rb_cntl = rb_bufsz << 1; 1724 rb_cntl = rb_bufsz << 1;
1725#ifdef __BIG_ENDIAN 1725#ifdef __BIG_ENDIAN
1726 rb_cntl |= DMA_RB_SWAP_ENABLE | DMA_RPTR_WRITEBACK_SWAP_ENABLE; 1726 rb_cntl |= DMA_RB_SWAP_ENABLE | DMA_RPTR_WRITEBACK_SWAP_ENABLE;