1 files changed, 6 insertions, 6 deletions

diff --git a/drivers/gpu/drm/radeon/ni.c b/drivers/gpu/drm/radeon/ni.c
index cbf57d75d925..99fbd793c08c 100644
--- a/drivers/gpu/drm/radeon/ni.c
+++ b/drivers/gpu/drm/radeon/ni.c
@@ -1187,7 +1187,8 @@ int cayman_cp_resume(struct radeon_device *rdev)
 
         /* Initialize the ring buffer's read and write pointers */
         WREG32(CP_RB0_CNTL, tmp | RB_RPTR_WR_ENA);
-        WREG32(CP_RB0_WPTR, 0);
+        rdev->cp.wptr = 0;
+        WREG32(CP_RB0_WPTR, rdev->cp.wptr);
 
         /* set the wb address wether it's enabled or not */
         WREG32(CP_RB0_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC);
@@ -1207,7 +1208,6 @@ int cayman_cp_resume(struct radeon_device *rdev)
         WREG32(CP_RB0_BASE, rdev->cp.gpu_addr >> 8);
 
         rdev->cp.rptr = RREG32(CP_RB0_RPTR);
-        rdev->cp.wptr = RREG32(CP_RB0_WPTR);
 
         /* ring1  - compute only */
         /* Set ring buffer size */
@@ -1220,7 +1220,8 @@ int cayman_cp_resume(struct radeon_device *rdev)
 
         /* Initialize the ring buffer's read and write pointers */
         WREG32(CP_RB1_CNTL, tmp | RB_RPTR_WR_ENA);
-        WREG32(CP_RB1_WPTR, 0);
+        rdev->cp1.wptr = 0;
+        WREG32(CP_RB1_WPTR, rdev->cp1.wptr);
 
         /* set the wb address wether it's enabled or not */
         WREG32(CP_RB1_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET) & 0xFFFFFFFC);
@@ -1232,7 +1233,6 @@ int cayman_cp_resume(struct radeon_device *rdev)
         WREG32(CP_RB1_BASE, rdev->cp1.gpu_addr >> 8);
 
         rdev->cp1.rptr = RREG32(CP_RB1_RPTR);
-        rdev->cp1.wptr = RREG32(CP_RB1_WPTR);
 
         /* ring2 - compute only */
         /* Set ring buffer size */
@@ -1245,7 +1245,8 @@ int cayman_cp_resume(struct radeon_device *rdev)
 
         /* Initialize the ring buffer's read and write pointers */
         WREG32(CP_RB2_CNTL, tmp | RB_RPTR_WR_ENA);
-        WREG32(CP_RB2_WPTR, 0);
+        rdev->cp2.wptr = 0;
+        WREG32(CP_RB2_WPTR, rdev->cp2.wptr);
 
         /* set the wb address wether it's enabled or not */
         WREG32(CP_RB2_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET) & 0xFFFFFFFC);
@@ -1257,7 +1258,6 @@ int cayman_cp_resume(struct radeon_device *rdev)
         WREG32(CP_RB2_BASE, rdev->cp2.gpu_addr >> 8);
 
         rdev->cp2.rptr = RREG32(CP_RB2_RPTR);
-        rdev->cp2.wptr = RREG32(CP_RB2_WPTR);
 
         /* start the rings */
         cayman_cp_start(rdev);