diff options
Diffstat (limited to 'drivers/gpu/drm/radeon/ni.c')
-rw-r--r-- | drivers/gpu/drm/radeon/ni.c | 44 |
1 files changed, 6 insertions, 38 deletions
diff --git a/drivers/gpu/drm/radeon/ni.c b/drivers/gpu/drm/radeon/ni.c index cbf57d75d925..8c79ca97753d 100644 --- a/drivers/gpu/drm/radeon/ni.c +++ b/drivers/gpu/drm/radeon/ni.c | |||
@@ -569,36 +569,6 @@ static u32 cayman_get_tile_pipe_to_backend_map(struct radeon_device *rdev, | |||
569 | return backend_map; | 569 | return backend_map; |
570 | } | 570 | } |
571 | 571 | ||
572 | static void cayman_program_channel_remap(struct radeon_device *rdev) | ||
573 | { | ||
574 | u32 tcp_chan_steer_lo, tcp_chan_steer_hi, mc_shared_chremap, tmp; | ||
575 | |||
576 | tmp = RREG32(MC_SHARED_CHMAP); | ||
577 | switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) { | ||
578 | case 0: | ||
579 | case 1: | ||
580 | case 2: | ||
581 | case 3: | ||
582 | default: | ||
583 | /* default mapping */ | ||
584 | mc_shared_chremap = 0x00fac688; | ||
585 | break; | ||
586 | } | ||
587 | |||
588 | switch (rdev->family) { | ||
589 | case CHIP_CAYMAN: | ||
590 | default: | ||
591 | //tcp_chan_steer_lo = 0x54763210 | ||
592 | tcp_chan_steer_lo = 0x76543210; | ||
593 | tcp_chan_steer_hi = 0x0000ba98; | ||
594 | break; | ||
595 | } | ||
596 | |||
597 | WREG32(TCP_CHAN_STEER_LO, tcp_chan_steer_lo); | ||
598 | WREG32(TCP_CHAN_STEER_HI, tcp_chan_steer_hi); | ||
599 | WREG32(MC_SHARED_CHREMAP, mc_shared_chremap); | ||
600 | } | ||
601 | |||
602 | static u32 cayman_get_disable_mask_per_asic(struct radeon_device *rdev, | 572 | static u32 cayman_get_disable_mask_per_asic(struct radeon_device *rdev, |
603 | u32 disable_mask_per_se, | 573 | u32 disable_mask_per_se, |
604 | u32 max_disable_mask_per_se, | 574 | u32 max_disable_mask_per_se, |
@@ -842,8 +812,6 @@ static void cayman_gpu_init(struct radeon_device *rdev) | |||
842 | WREG32(DMIF_ADDR_CONFIG, gb_addr_config); | 812 | WREG32(DMIF_ADDR_CONFIG, gb_addr_config); |
843 | WREG32(HDP_ADDR_CONFIG, gb_addr_config); | 813 | WREG32(HDP_ADDR_CONFIG, gb_addr_config); |
844 | 814 | ||
845 | cayman_program_channel_remap(rdev); | ||
846 | |||
847 | /* primary versions */ | 815 | /* primary versions */ |
848 | WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable); | 816 | WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable); |
849 | WREG32(CC_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable); | 817 | WREG32(CC_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable); |
@@ -1187,7 +1155,8 @@ int cayman_cp_resume(struct radeon_device *rdev) | |||
1187 | 1155 | ||
1188 | /* Initialize the ring buffer's read and write pointers */ | 1156 | /* Initialize the ring buffer's read and write pointers */ |
1189 | WREG32(CP_RB0_CNTL, tmp | RB_RPTR_WR_ENA); | 1157 | WREG32(CP_RB0_CNTL, tmp | RB_RPTR_WR_ENA); |
1190 | WREG32(CP_RB0_WPTR, 0); | 1158 | rdev->cp.wptr = 0; |
1159 | WREG32(CP_RB0_WPTR, rdev->cp.wptr); | ||
1191 | 1160 | ||
1192 | /* set the wb address wether it's enabled or not */ | 1161 | /* set the wb address wether it's enabled or not */ |
1193 | WREG32(CP_RB0_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC); | 1162 | WREG32(CP_RB0_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC); |
@@ -1207,7 +1176,6 @@ int cayman_cp_resume(struct radeon_device *rdev) | |||
1207 | WREG32(CP_RB0_BASE, rdev->cp.gpu_addr >> 8); | 1176 | WREG32(CP_RB0_BASE, rdev->cp.gpu_addr >> 8); |
1208 | 1177 | ||
1209 | rdev->cp.rptr = RREG32(CP_RB0_RPTR); | 1178 | rdev->cp.rptr = RREG32(CP_RB0_RPTR); |
1210 | rdev->cp.wptr = RREG32(CP_RB0_WPTR); | ||
1211 | 1179 | ||
1212 | /* ring1 - compute only */ | 1180 | /* ring1 - compute only */ |
1213 | /* Set ring buffer size */ | 1181 | /* Set ring buffer size */ |
@@ -1220,7 +1188,8 @@ int cayman_cp_resume(struct radeon_device *rdev) | |||
1220 | 1188 | ||
1221 | /* Initialize the ring buffer's read and write pointers */ | 1189 | /* Initialize the ring buffer's read and write pointers */ |
1222 | WREG32(CP_RB1_CNTL, tmp | RB_RPTR_WR_ENA); | 1190 | WREG32(CP_RB1_CNTL, tmp | RB_RPTR_WR_ENA); |
1223 | WREG32(CP_RB1_WPTR, 0); | 1191 | rdev->cp1.wptr = 0; |
1192 | WREG32(CP_RB1_WPTR, rdev->cp1.wptr); | ||
1224 | 1193 | ||
1225 | /* set the wb address wether it's enabled or not */ | 1194 | /* set the wb address wether it's enabled or not */ |
1226 | WREG32(CP_RB1_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET) & 0xFFFFFFFC); | 1195 | WREG32(CP_RB1_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP1_RPTR_OFFSET) & 0xFFFFFFFC); |
@@ -1232,7 +1201,6 @@ int cayman_cp_resume(struct radeon_device *rdev) | |||
1232 | WREG32(CP_RB1_BASE, rdev->cp1.gpu_addr >> 8); | 1201 | WREG32(CP_RB1_BASE, rdev->cp1.gpu_addr >> 8); |
1233 | 1202 | ||
1234 | rdev->cp1.rptr = RREG32(CP_RB1_RPTR); | 1203 | rdev->cp1.rptr = RREG32(CP_RB1_RPTR); |
1235 | rdev->cp1.wptr = RREG32(CP_RB1_WPTR); | ||
1236 | 1204 | ||
1237 | /* ring2 - compute only */ | 1205 | /* ring2 - compute only */ |
1238 | /* Set ring buffer size */ | 1206 | /* Set ring buffer size */ |
@@ -1245,7 +1213,8 @@ int cayman_cp_resume(struct radeon_device *rdev) | |||
1245 | 1213 | ||
1246 | /* Initialize the ring buffer's read and write pointers */ | 1214 | /* Initialize the ring buffer's read and write pointers */ |
1247 | WREG32(CP_RB2_CNTL, tmp | RB_RPTR_WR_ENA); | 1215 | WREG32(CP_RB2_CNTL, tmp | RB_RPTR_WR_ENA); |
1248 | WREG32(CP_RB2_WPTR, 0); | 1216 | rdev->cp2.wptr = 0; |
1217 | WREG32(CP_RB2_WPTR, rdev->cp2.wptr); | ||
1249 | 1218 | ||
1250 | /* set the wb address wether it's enabled or not */ | 1219 | /* set the wb address wether it's enabled or not */ |
1251 | WREG32(CP_RB2_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET) & 0xFFFFFFFC); | 1220 | WREG32(CP_RB2_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP2_RPTR_OFFSET) & 0xFFFFFFFC); |
@@ -1257,7 +1226,6 @@ int cayman_cp_resume(struct radeon_device *rdev) | |||
1257 | WREG32(CP_RB2_BASE, rdev->cp2.gpu_addr >> 8); | 1226 | WREG32(CP_RB2_BASE, rdev->cp2.gpu_addr >> 8); |
1258 | 1227 | ||
1259 | rdev->cp2.rptr = RREG32(CP_RB2_RPTR); | 1228 | rdev->cp2.rptr = RREG32(CP_RB2_RPTR); |
1260 | rdev->cp2.wptr = RREG32(CP_RB2_WPTR); | ||
1261 | 1229 | ||
1262 | /* start the rings */ | 1230 | /* start the rings */ |
1263 | cayman_cp_start(rdev); | 1231 | cayman_cp_start(rdev); |