diff options
Diffstat (limited to 'drivers/gpu/drm/radeon/evergreend.h')
-rw-r--r-- | drivers/gpu/drm/radeon/evergreend.h | 46 |
1 files changed, 45 insertions, 1 deletions
diff --git a/drivers/gpu/drm/radeon/evergreend.h b/drivers/gpu/drm/radeon/evergreend.h index 35e61539b5f8..c0df1cac9485 100644 --- a/drivers/gpu/drm/radeon/evergreend.h +++ b/drivers/gpu/drm/radeon/evergreend.h | |||
@@ -1323,7 +1323,48 @@ | |||
1323 | #define DMA_PACKET_CONSTANT_FILL 0xd | 1323 | #define DMA_PACKET_CONSTANT_FILL 0xd |
1324 | #define DMA_PACKET_NOP 0xf | 1324 | #define DMA_PACKET_NOP 0xf |
1325 | 1325 | ||
1326 | /* PCIE link stuff */ | 1326 | /* PIF PHY0 indirect regs */ |
1327 | #define PB0_PIF_CNTL 0x10 | ||
1328 | # define LS2_EXIT_TIME(x) ((x) << 17) | ||
1329 | # define LS2_EXIT_TIME_MASK (0x7 << 17) | ||
1330 | # define LS2_EXIT_TIME_SHIFT 17 | ||
1331 | #define PB0_PIF_PAIRING 0x11 | ||
1332 | # define MULTI_PIF (1 << 25) | ||
1333 | #define PB0_PIF_PWRDOWN_0 0x12 | ||
1334 | # define PLL_POWER_STATE_IN_TXS2_0(x) ((x) << 7) | ||
1335 | # define PLL_POWER_STATE_IN_TXS2_0_MASK (0x7 << 7) | ||
1336 | # define PLL_POWER_STATE_IN_TXS2_0_SHIFT 7 | ||
1337 | # define PLL_POWER_STATE_IN_OFF_0(x) ((x) << 10) | ||
1338 | # define PLL_POWER_STATE_IN_OFF_0_MASK (0x7 << 10) | ||
1339 | # define PLL_POWER_STATE_IN_OFF_0_SHIFT 10 | ||
1340 | # define PLL_RAMP_UP_TIME_0(x) ((x) << 24) | ||
1341 | # define PLL_RAMP_UP_TIME_0_MASK (0x7 << 24) | ||
1342 | # define PLL_RAMP_UP_TIME_0_SHIFT 24 | ||
1343 | #define PB0_PIF_PWRDOWN_1 0x13 | ||
1344 | # define PLL_POWER_STATE_IN_TXS2_1(x) ((x) << 7) | ||
1345 | # define PLL_POWER_STATE_IN_TXS2_1_MASK (0x7 << 7) | ||
1346 | # define PLL_POWER_STATE_IN_TXS2_1_SHIFT 7 | ||
1347 | # define PLL_POWER_STATE_IN_OFF_1(x) ((x) << 10) | ||
1348 | # define PLL_POWER_STATE_IN_OFF_1_MASK (0x7 << 10) | ||
1349 | # define PLL_POWER_STATE_IN_OFF_1_SHIFT 10 | ||
1350 | # define PLL_RAMP_UP_TIME_1(x) ((x) << 24) | ||
1351 | # define PLL_RAMP_UP_TIME_1_MASK (0x7 << 24) | ||
1352 | # define PLL_RAMP_UP_TIME_1_SHIFT 24 | ||
1353 | /* PIF PHY1 indirect regs */ | ||
1354 | #define PB1_PIF_CNTL 0x10 | ||
1355 | #define PB1_PIF_PAIRING 0x11 | ||
1356 | #define PB1_PIF_PWRDOWN_0 0x12 | ||
1357 | #define PB1_PIF_PWRDOWN_1 0x13 | ||
1358 | /* PCIE PORT indirect regs */ | ||
1359 | #define PCIE_LC_CNTL 0xa0 | ||
1360 | # define LC_L0S_INACTIVITY(x) ((x) << 8) | ||
1361 | # define LC_L0S_INACTIVITY_MASK (0xf << 8) | ||
1362 | # define LC_L0S_INACTIVITY_SHIFT 8 | ||
1363 | # define LC_L1_INACTIVITY(x) ((x) << 12) | ||
1364 | # define LC_L1_INACTIVITY_MASK (0xf << 12) | ||
1365 | # define LC_L1_INACTIVITY_SHIFT 12 | ||
1366 | # define LC_PMI_TO_L1_DIS (1 << 16) | ||
1367 | # define LC_ASPM_TO_L1_DIS (1 << 24) | ||
1327 | #define PCIE_LC_TRAINING_CNTL 0xa1 /* PCIE_P */ | 1368 | #define PCIE_LC_TRAINING_CNTL 0xa1 /* PCIE_P */ |
1328 | #define PCIE_LC_LINK_WIDTH_CNTL 0xa2 /* PCIE_P */ | 1369 | #define PCIE_LC_LINK_WIDTH_CNTL 0xa2 /* PCIE_P */ |
1329 | # define LC_LINK_WIDTH_SHIFT 0 | 1370 | # define LC_LINK_WIDTH_SHIFT 0 |
@@ -1343,6 +1384,9 @@ | |||
1343 | # define LC_SHORT_RECONFIG_EN (1 << 11) | 1384 | # define LC_SHORT_RECONFIG_EN (1 << 11) |
1344 | # define LC_UPCONFIGURE_SUPPORT (1 << 12) | 1385 | # define LC_UPCONFIGURE_SUPPORT (1 << 12) |
1345 | # define LC_UPCONFIGURE_DIS (1 << 13) | 1386 | # define LC_UPCONFIGURE_DIS (1 << 13) |
1387 | # define LC_DYN_LANES_PWR_STATE(x) ((x) << 21) | ||
1388 | # define LC_DYN_LANES_PWR_STATE_MASK (0x3 << 21) | ||
1389 | # define LC_DYN_LANES_PWR_STATE_SHIFT 21 | ||
1346 | #define PCIE_LC_SPEED_CNTL 0xa4 /* PCIE_P */ | 1390 | #define PCIE_LC_SPEED_CNTL 0xa4 /* PCIE_P */ |
1347 | # define LC_GEN2_EN_STRAP (1 << 0) | 1391 | # define LC_GEN2_EN_STRAP (1 << 0) |
1348 | # define LC_TARGET_LINK_SPEED_OVERRIDE_EN (1 << 1) | 1392 | # define LC_TARGET_LINK_SPEED_OVERRIDE_EN (1 << 1) |