diff options
Diffstat (limited to 'drivers/gpu/drm/radeon/evergreend.h')
-rw-r--r-- | drivers/gpu/drm/radeon/evergreend.h | 65 |
1 files changed, 63 insertions, 2 deletions
diff --git a/drivers/gpu/drm/radeon/evergreend.h b/drivers/gpu/drm/radeon/evergreend.h index e00039e59a75..b502216d42af 100644 --- a/drivers/gpu/drm/radeon/evergreend.h +++ b/drivers/gpu/drm/radeon/evergreend.h | |||
@@ -242,6 +242,7 @@ | |||
242 | #define PA_CL_ENHANCE 0x8A14 | 242 | #define PA_CL_ENHANCE 0x8A14 |
243 | #define CLIP_VTX_REORDER_ENA (1 << 0) | 243 | #define CLIP_VTX_REORDER_ENA (1 << 0) |
244 | #define NUM_CLIP_SEQ(x) ((x) << 1) | 244 | #define NUM_CLIP_SEQ(x) ((x) << 1) |
245 | #define PA_SC_ENHANCE 0x8BF0 | ||
245 | #define PA_SC_AA_CONFIG 0x28C04 | 246 | #define PA_SC_AA_CONFIG 0x28C04 |
246 | #define MSAA_NUM_SAMPLES_SHIFT 0 | 247 | #define MSAA_NUM_SAMPLES_SHIFT 0 |
247 | #define MSAA_NUM_SAMPLES_MASK 0x3 | 248 | #define MSAA_NUM_SAMPLES_MASK 0x3 |
@@ -319,6 +320,8 @@ | |||
319 | #define SQ_GPR_RESOURCE_MGMT_3 0x8C0C | 320 | #define SQ_GPR_RESOURCE_MGMT_3 0x8C0C |
320 | #define NUM_HS_GPRS(x) ((x) << 0) | 321 | #define NUM_HS_GPRS(x) ((x) << 0) |
321 | #define NUM_LS_GPRS(x) ((x) << 16) | 322 | #define NUM_LS_GPRS(x) ((x) << 16) |
323 | #define SQ_GLOBAL_GPR_RESOURCE_MGMT_1 0x8C10 | ||
324 | #define SQ_GLOBAL_GPR_RESOURCE_MGMT_2 0x8C14 | ||
322 | #define SQ_THREAD_RESOURCE_MGMT 0x8C18 | 325 | #define SQ_THREAD_RESOURCE_MGMT 0x8C18 |
323 | #define NUM_PS_THREADS(x) ((x) << 0) | 326 | #define NUM_PS_THREADS(x) ((x) << 0) |
324 | #define NUM_VS_THREADS(x) ((x) << 8) | 327 | #define NUM_VS_THREADS(x) ((x) << 8) |
@@ -337,6 +340,10 @@ | |||
337 | #define NUM_HS_STACK_ENTRIES(x) ((x) << 0) | 340 | #define NUM_HS_STACK_ENTRIES(x) ((x) << 0) |
338 | #define NUM_LS_STACK_ENTRIES(x) ((x) << 16) | 341 | #define NUM_LS_STACK_ENTRIES(x) ((x) << 16) |
339 | #define SQ_DYN_GPR_CNTL_PS_FLUSH_REQ 0x8D8C | 342 | #define SQ_DYN_GPR_CNTL_PS_FLUSH_REQ 0x8D8C |
343 | #define SQ_DYN_GPR_SIMD_LOCK_EN 0x8D94 | ||
344 | #define SQ_STATIC_THREAD_MGMT_1 0x8E20 | ||
345 | #define SQ_STATIC_THREAD_MGMT_2 0x8E24 | ||
346 | #define SQ_STATIC_THREAD_MGMT_3 0x8E28 | ||
340 | #define SQ_LDS_RESOURCE_MGMT 0x8E2C | 347 | #define SQ_LDS_RESOURCE_MGMT 0x8E2C |
341 | 348 | ||
342 | #define SQ_MS_FIFO_SIZES 0x8CF0 | 349 | #define SQ_MS_FIFO_SIZES 0x8CF0 |
@@ -691,6 +698,7 @@ | |||
691 | #define PACKET3_DRAW_INDEX_MULTI_ELEMENT 0x36 | 698 | #define PACKET3_DRAW_INDEX_MULTI_ELEMENT 0x36 |
692 | #define PACKET3_MEM_SEMAPHORE 0x39 | 699 | #define PACKET3_MEM_SEMAPHORE 0x39 |
693 | #define PACKET3_MPEG_INDEX 0x3A | 700 | #define PACKET3_MPEG_INDEX 0x3A |
701 | #define PACKET3_COPY_DW 0x3B | ||
694 | #define PACKET3_WAIT_REG_MEM 0x3C | 702 | #define PACKET3_WAIT_REG_MEM 0x3C |
695 | #define PACKET3_MEM_WRITE 0x3D | 703 | #define PACKET3_MEM_WRITE 0x3D |
696 | #define PACKET3_INDIRECT_BUFFER 0x32 | 704 | #define PACKET3_INDIRECT_BUFFER 0x32 |
@@ -768,6 +776,8 @@ | |||
768 | #define SQ_TEX_VTX_VALID_TEXTURE 0x2 | 776 | #define SQ_TEX_VTX_VALID_TEXTURE 0x2 |
769 | #define SQ_TEX_VTX_VALID_BUFFER 0x3 | 777 | #define SQ_TEX_VTX_VALID_BUFFER 0x3 |
770 | 778 | ||
779 | #define VGT_VTX_VECT_EJECT_REG 0x88b0 | ||
780 | |||
771 | #define SQ_CONST_MEM_BASE 0x8df8 | 781 | #define SQ_CONST_MEM_BASE 0x8df8 |
772 | 782 | ||
773 | #define SQ_ESGS_RING_BASE 0x8c40 | 783 | #define SQ_ESGS_RING_BASE 0x8c40 |
@@ -892,8 +902,27 @@ | |||
892 | #define PA_SC_SCREEN_SCISSOR_TL 0x28030 | 902 | #define PA_SC_SCREEN_SCISSOR_TL 0x28030 |
893 | #define PA_SC_GENERIC_SCISSOR_TL 0x28240 | 903 | #define PA_SC_GENERIC_SCISSOR_TL 0x28240 |
894 | #define PA_SC_WINDOW_SCISSOR_TL 0x28204 | 904 | #define PA_SC_WINDOW_SCISSOR_TL 0x28204 |
895 | #define VGT_PRIMITIVE_TYPE 0x8958 | ||
896 | 905 | ||
906 | #define VGT_PRIMITIVE_TYPE 0x8958 | ||
907 | #define VGT_INDEX_TYPE 0x895C | ||
908 | |||
909 | #define VGT_NUM_INDICES 0x8970 | ||
910 | |||
911 | #define VGT_COMPUTE_DIM_X 0x8990 | ||
912 | #define VGT_COMPUTE_DIM_Y 0x8994 | ||
913 | #define VGT_COMPUTE_DIM_Z 0x8998 | ||
914 | #define VGT_COMPUTE_START_X 0x899C | ||
915 | #define VGT_COMPUTE_START_Y 0x89A0 | ||
916 | #define VGT_COMPUTE_START_Z 0x89A4 | ||
917 | #define VGT_COMPUTE_INDEX 0x89A8 | ||
918 | #define VGT_COMPUTE_THREAD_GROUP_SIZE 0x89AC | ||
919 | #define VGT_HS_OFFCHIP_PARAM 0x89B0 | ||
920 | |||
921 | #define DB_DEBUG 0x9830 | ||
922 | #define DB_DEBUG2 0x9834 | ||
923 | #define DB_DEBUG3 0x9838 | ||
924 | #define DB_DEBUG4 0x983C | ||
925 | #define DB_WATERMARKS 0x9854 | ||
897 | #define DB_DEPTH_CONTROL 0x28800 | 926 | #define DB_DEPTH_CONTROL 0x28800 |
898 | #define DB_DEPTH_VIEW 0x28008 | 927 | #define DB_DEPTH_VIEW 0x28008 |
899 | #define DB_HTILE_DATA_BASE 0x28014 | 928 | #define DB_HTILE_DATA_BASE 0x28014 |
@@ -1189,8 +1218,40 @@ | |||
1189 | #define SQ_VTX_CONSTANT_WORD6_0 0x30018 | 1218 | #define SQ_VTX_CONSTANT_WORD6_0 0x30018 |
1190 | #define SQ_VTX_CONSTANT_WORD7_0 0x3001c | 1219 | #define SQ_VTX_CONSTANT_WORD7_0 0x3001c |
1191 | 1220 | ||
1221 | #define TD_PS_BORDER_COLOR_INDEX 0xA400 | ||
1222 | #define TD_PS_BORDER_COLOR_RED 0xA404 | ||
1223 | #define TD_PS_BORDER_COLOR_GREEN 0xA408 | ||
1224 | #define TD_PS_BORDER_COLOR_BLUE 0xA40C | ||
1225 | #define TD_PS_BORDER_COLOR_ALPHA 0xA410 | ||
1226 | #define TD_VS_BORDER_COLOR_INDEX 0xA414 | ||
1227 | #define TD_VS_BORDER_COLOR_RED 0xA418 | ||
1228 | #define TD_VS_BORDER_COLOR_GREEN 0xA41C | ||
1229 | #define TD_VS_BORDER_COLOR_BLUE 0xA420 | ||
1230 | #define TD_VS_BORDER_COLOR_ALPHA 0xA424 | ||
1231 | #define TD_GS_BORDER_COLOR_INDEX 0xA428 | ||
1232 | #define TD_GS_BORDER_COLOR_RED 0xA42C | ||
1233 | #define TD_GS_BORDER_COLOR_GREEN 0xA430 | ||
1234 | #define TD_GS_BORDER_COLOR_BLUE 0xA434 | ||
1235 | #define TD_GS_BORDER_COLOR_ALPHA 0xA438 | ||
1236 | #define TD_HS_BORDER_COLOR_INDEX 0xA43C | ||
1237 | #define TD_HS_BORDER_COLOR_RED 0xA440 | ||
1238 | #define TD_HS_BORDER_COLOR_GREEN 0xA444 | ||
1239 | #define TD_HS_BORDER_COLOR_BLUE 0xA448 | ||
1240 | #define TD_HS_BORDER_COLOR_ALPHA 0xA44C | ||
1241 | #define TD_LS_BORDER_COLOR_INDEX 0xA450 | ||
1242 | #define TD_LS_BORDER_COLOR_RED 0xA454 | ||
1243 | #define TD_LS_BORDER_COLOR_GREEN 0xA458 | ||
1244 | #define TD_LS_BORDER_COLOR_BLUE 0xA45C | ||
1245 | #define TD_LS_BORDER_COLOR_ALPHA 0xA460 | ||
1246 | #define TD_CS_BORDER_COLOR_INDEX 0xA464 | ||
1247 | #define TD_CS_BORDER_COLOR_RED 0xA468 | ||
1248 | #define TD_CS_BORDER_COLOR_GREEN 0xA46C | ||
1249 | #define TD_CS_BORDER_COLOR_BLUE 0xA470 | ||
1250 | #define TD_CS_BORDER_COLOR_ALPHA 0xA474 | ||
1251 | |||
1192 | /* cayman 3D regs */ | 1252 | /* cayman 3D regs */ |
1193 | #define CAYMAN_VGT_OFFCHIP_LDS_BASE 0x89B0 | 1253 | #define CAYMAN_VGT_OFFCHIP_LDS_BASE 0x89B4 |
1254 | #define CAYMAN_SQ_EX_ALLOC_TABLE_SLOTS 0x8E48 | ||
1194 | #define CAYMAN_DB_EQAA 0x28804 | 1255 | #define CAYMAN_DB_EQAA 0x28804 |
1195 | #define CAYMAN_DB_DEPTH_INFO 0x2803C | 1256 | #define CAYMAN_DB_DEPTH_INFO 0x2803C |
1196 | #define CAYMAN_PA_SC_AA_CONFIG 0x28BE0 | 1257 | #define CAYMAN_PA_SC_AA_CONFIG 0x28BE0 |