diff options
Diffstat (limited to 'drivers/gpu/drm/radeon/evergreend.h')
| -rw-r--r-- | drivers/gpu/drm/radeon/evergreend.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/gpu/drm/radeon/evergreend.h b/drivers/gpu/drm/radeon/evergreend.h index 17f990798992..f9c7963b3ee6 100644 --- a/drivers/gpu/drm/radeon/evergreend.h +++ b/drivers/gpu/drm/radeon/evergreend.h | |||
| @@ -82,12 +82,16 @@ | |||
| 82 | #define CG_SPLL_FUNC_CNTL_2 0x604 | 82 | #define CG_SPLL_FUNC_CNTL_2 0x604 |
| 83 | #define SCLK_MUX_SEL(x) ((x) << 0) | 83 | #define SCLK_MUX_SEL(x) ((x) << 0) |
| 84 | #define SCLK_MUX_SEL_MASK (0x1ff << 0) | 84 | #define SCLK_MUX_SEL_MASK (0x1ff << 0) |
| 85 | #define SCLK_MUX_UPDATE (1 << 26) | ||
| 85 | #define CG_SPLL_FUNC_CNTL_3 0x608 | 86 | #define CG_SPLL_FUNC_CNTL_3 0x608 |
| 86 | #define SPLL_FB_DIV(x) ((x) << 0) | 87 | #define SPLL_FB_DIV(x) ((x) << 0) |
| 87 | #define SPLL_FB_DIV_MASK (0x3ffffff << 0) | 88 | #define SPLL_FB_DIV_MASK (0x3ffffff << 0) |
| 88 | #define SPLL_DITHEN (1 << 28) | 89 | #define SPLL_DITHEN (1 << 28) |
| 90 | #define CG_SPLL_STATUS 0x60c | ||
| 91 | #define SPLL_CHG_STATUS (1 << 1) | ||
| 89 | 92 | ||
| 90 | #define MPLL_CNTL_MODE 0x61c | 93 | #define MPLL_CNTL_MODE 0x61c |
| 94 | # define MPLL_MCLK_SEL (1 << 11) | ||
| 91 | # define SS_SSEN (1 << 24) | 95 | # define SS_SSEN (1 << 24) |
| 92 | # define SS_DSMODE_EN (1 << 25) | 96 | # define SS_DSMODE_EN (1 << 25) |
| 93 | 97 | ||