diff options
Diffstat (limited to 'drivers/gpu/drm/radeon/evergreend.h')
-rw-r--r-- | drivers/gpu/drm/radeon/evergreend.h | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/drivers/gpu/drm/radeon/evergreend.h b/drivers/gpu/drm/radeon/evergreend.h index 9b7532dd30f7..113c70cc8b39 100644 --- a/drivers/gpu/drm/radeon/evergreend.h +++ b/drivers/gpu/drm/radeon/evergreend.h | |||
@@ -412,6 +412,19 @@ | |||
412 | #define SOFT_RESET_REGBB (1 << 22) | 412 | #define SOFT_RESET_REGBB (1 << 22) |
413 | #define SOFT_RESET_ORB (1 << 23) | 413 | #define SOFT_RESET_ORB (1 << 23) |
414 | 414 | ||
415 | /* display watermarks */ | ||
416 | #define DC_LB_MEMORY_SPLIT 0x6b0c | ||
417 | #define PRIORITY_A_CNT 0x6b18 | ||
418 | #define PRIORITY_MARK_MASK 0x7fff | ||
419 | #define PRIORITY_OFF (1 << 16) | ||
420 | #define PRIORITY_ALWAYS_ON (1 << 20) | ||
421 | #define PRIORITY_B_CNT 0x6b1c | ||
422 | #define PIPE0_ARBITRATION_CONTROL3 0x0bf0 | ||
423 | # define LATENCY_WATERMARK_MASK(x) ((x) << 16) | ||
424 | #define PIPE0_LATENCY_CONTROL 0x0bf4 | ||
425 | # define LATENCY_LOW_WATERMARK(x) ((x) << 0) | ||
426 | # define LATENCY_HIGH_WATERMARK(x) ((x) << 16) | ||
427 | |||
415 | #define IH_RB_CNTL 0x3e00 | 428 | #define IH_RB_CNTL 0x3e00 |
416 | # define IH_RB_ENABLE (1 << 0) | 429 | # define IH_RB_ENABLE (1 << 0) |
417 | # define IH_IB_SIZE(x) ((x) << 1) /* log2 */ | 430 | # define IH_IB_SIZE(x) ((x) << 1) /* log2 */ |
@@ -645,6 +658,8 @@ | |||
645 | #define PACKET3_EVENT_WRITE_EOP 0x47 | 658 | #define PACKET3_EVENT_WRITE_EOP 0x47 |
646 | #define PACKET3_EVENT_WRITE_EOS 0x48 | 659 | #define PACKET3_EVENT_WRITE_EOS 0x48 |
647 | #define PACKET3_PREAMBLE_CNTL 0x4A | 660 | #define PACKET3_PREAMBLE_CNTL 0x4A |
661 | # define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28) | ||
662 | # define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28) | ||
648 | #define PACKET3_RB_OFFSET 0x4B | 663 | #define PACKET3_RB_OFFSET 0x4B |
649 | #define PACKET3_ALU_PS_CONST_BUFFER_COPY 0x4C | 664 | #define PACKET3_ALU_PS_CONST_BUFFER_COPY 0x4C |
650 | #define PACKET3_ALU_VS_CONST_BUFFER_COPY 0x4D | 665 | #define PACKET3_ALU_VS_CONST_BUFFER_COPY 0x4D |
@@ -802,6 +817,11 @@ | |||
802 | #define SQ_ALU_CONST_CACHE_LS_14 0x28f78 | 817 | #define SQ_ALU_CONST_CACHE_LS_14 0x28f78 |
803 | #define SQ_ALU_CONST_CACHE_LS_15 0x28f7c | 818 | #define SQ_ALU_CONST_CACHE_LS_15 0x28f7c |
804 | 819 | ||
820 | #define PA_SC_SCREEN_SCISSOR_TL 0x28030 | ||
821 | #define PA_SC_GENERIC_SCISSOR_TL 0x28240 | ||
822 | #define PA_SC_WINDOW_SCISSOR_TL 0x28204 | ||
823 | #define VGT_PRIMITIVE_TYPE 0x8958 | ||
824 | |||
805 | #define DB_DEPTH_CONTROL 0x28800 | 825 | #define DB_DEPTH_CONTROL 0x28800 |
806 | #define DB_DEPTH_VIEW 0x28008 | 826 | #define DB_DEPTH_VIEW 0x28008 |
807 | #define DB_HTILE_DATA_BASE 0x28014 | 827 | #define DB_HTILE_DATA_BASE 0x28014 |