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path: root/drivers/gpu/drm/radeon/evergreen.c
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Diffstat (limited to 'drivers/gpu/drm/radeon/evergreen.c')
-rw-r--r--drivers/gpu/drm/radeon/evergreen.c14
1 files changed, 8 insertions, 6 deletions
diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
index dc0a5b56c81a..e8a746712b5b 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -1404,7 +1404,8 @@ int evergreen_cp_resume(struct radeon_device *rdev)
1404 /* Initialize the ring buffer's read and write pointers */ 1404 /* Initialize the ring buffer's read and write pointers */
1405 WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA); 1405 WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
1406 WREG32(CP_RB_RPTR_WR, 0); 1406 WREG32(CP_RB_RPTR_WR, 0);
1407 WREG32(CP_RB_WPTR, 0); 1407 rdev->cp.wptr = 0;
1408 WREG32(CP_RB_WPTR, rdev->cp.wptr);
1408 1409
1409 /* set the wb address wether it's enabled or not */ 1410 /* set the wb address wether it's enabled or not */
1410 WREG32(CP_RB_RPTR_ADDR, 1411 WREG32(CP_RB_RPTR_ADDR,
@@ -1426,7 +1427,6 @@ int evergreen_cp_resume(struct radeon_device *rdev)
1426 WREG32(CP_DEBUG, (1 << 27) | (1 << 28)); 1427 WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
1427 1428
1428 rdev->cp.rptr = RREG32(CP_RB_RPTR); 1429 rdev->cp.rptr = RREG32(CP_RB_RPTR);
1429 rdev->cp.wptr = RREG32(CP_RB_WPTR);
1430 1430
1431 evergreen_cp_start(rdev); 1431 evergreen_cp_start(rdev);
1432 rdev->cp.ready = true; 1432 rdev->cp.ready = true;
@@ -3171,21 +3171,23 @@ int evergreen_suspend(struct radeon_device *rdev)
3171} 3171}
3172 3172
3173int evergreen_copy_blit(struct radeon_device *rdev, 3173int evergreen_copy_blit(struct radeon_device *rdev,
3174 uint64_t src_offset, uint64_t dst_offset, 3174 uint64_t src_offset,
3175 unsigned num_pages, struct radeon_fence *fence) 3175 uint64_t dst_offset,
3176 unsigned num_gpu_pages,
3177 struct radeon_fence *fence)
3176{ 3178{
3177 int r; 3179 int r;
3178 3180
3179 mutex_lock(&rdev->r600_blit.mutex); 3181 mutex_lock(&rdev->r600_blit.mutex);
3180 rdev->r600_blit.vb_ib = NULL; 3182 rdev->r600_blit.vb_ib = NULL;
3181 r = evergreen_blit_prepare_copy(rdev, num_pages * RADEON_GPU_PAGE_SIZE); 3183 r = evergreen_blit_prepare_copy(rdev, num_gpu_pages * RADEON_GPU_PAGE_SIZE);
3182 if (r) { 3184 if (r) {
3183 if (rdev->r600_blit.vb_ib) 3185 if (rdev->r600_blit.vb_ib)
3184 radeon_ib_free(rdev, &rdev->r600_blit.vb_ib); 3186 radeon_ib_free(rdev, &rdev->r600_blit.vb_ib);
3185 mutex_unlock(&rdev->r600_blit.mutex); 3187 mutex_unlock(&rdev->r600_blit.mutex);
3186 return r; 3188 return r;
3187 } 3189 }
3188 evergreen_kms_blit_copy(rdev, src_offset, dst_offset, num_pages * RADEON_GPU_PAGE_SIZE); 3190 evergreen_kms_blit_copy(rdev, src_offset, dst_offset, num_gpu_pages * RADEON_GPU_PAGE_SIZE);
3189 evergreen_blit_done_copy(rdev, fence); 3191 evergreen_blit_done_copy(rdev, fence);
3190 mutex_unlock(&rdev->r600_blit.mutex); 3192 mutex_unlock(&rdev->r600_blit.mutex);
3191 return 0; 3193 return 0;