1 files changed, 9 insertions, 2 deletions

diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
index a1f49c5fd74b..219942c660d7 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -1330,6 +1330,8 @@ void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *sav
                                         break;
                                 udelay(1);
                         }
+                } else {
+                        save->crtc_enabled[i] = false;
                 }
         }
 
@@ -1372,7 +1374,7 @@ void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *s
         WREG32(BIF_FB_EN, FB_READ_EN | FB_WRITE_EN);
 
         for (i = 0; i < rdev->num_crtc; i++) {
-                if (save->crtc_enabled) {
+                if (save->crtc_enabled[i]) {
                         if (ASIC_IS_DCE6(rdev)) {
                                 tmp = RREG32(EVERGREEN_CRTC_BLANK_CONTROL + crtc_offsets[i]);
                                 tmp |= EVERGREEN_CRTC_BLANK_DATA_EN;
@@ -3431,9 +3433,14 @@ void evergreen_pcie_gen2_enable(struct radeon_device *rdev)
         if (!(mask & DRM_PCIE_SPEED_50))
                 return;
 
+        speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
+        if (speed_cntl & LC_CURRENT_DATA_RATE) {
+                DRM_INFO("PCIE gen 2 link speeds already enabled\n");
+                return;
+        }
+
         DRM_INFO("enabling PCIE gen 2 link speeds, disable with radeon.pcie_gen2=0\n");
 
-        speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
         if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) ||
             (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) {