1 files changed, 71 insertions, 10 deletions

diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
index f58254a3fb01..cfa372cb1cb3 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -43,6 +43,37 @@ void evergreen_pcie_gen2_enable(struct radeon_device *rdev);
 extern void cayman_cp_int_cntl_setup(struct radeon_device *rdev,
                                      int ring, u32 cp_int_cntl);
 
+void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
+                             unsigned *bankh, unsigned *mtaspect,
+                             unsigned *tile_split)
+{
+        *bankw = (tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK;
+        *bankh = (tiling_flags >> RADEON_TILING_EG_BANKH_SHIFT) & RADEON_TILING_EG_BANKH_MASK;
+        *mtaspect = (tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK;
+        *tile_split = (tiling_flags >> RADEON_TILING_EG_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_TILE_SPLIT_MASK;
+        switch (*bankw) {
+        default:
+        case 1: *bankw = EVERGREEN_ADDR_SURF_BANK_WIDTH_1; break;
+        case 2: *bankw = EVERGREEN_ADDR_SURF_BANK_WIDTH_2; break;
+        case 4: *bankw = EVERGREEN_ADDR_SURF_BANK_WIDTH_4; break;
+        case 8: *bankw = EVERGREEN_ADDR_SURF_BANK_WIDTH_8; break;
+        }
+        switch (*bankh) {
+        default:
+        case 1: *bankh = EVERGREEN_ADDR_SURF_BANK_HEIGHT_1; break;
+        case 2: *bankh = EVERGREEN_ADDR_SURF_BANK_HEIGHT_2; break;
+        case 4: *bankh = EVERGREEN_ADDR_SURF_BANK_HEIGHT_4; break;
+        case 8: *bankh = EVERGREEN_ADDR_SURF_BANK_HEIGHT_8; break;
+        }
+        switch (*mtaspect) {
+        default:
+        case 1: *mtaspect = EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_1; break;
+        case 2: *mtaspect = EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_2; break;
+        case 4: *mtaspect = EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_4; break;
+        case 8: *mtaspect = EVERGREEN_ADDR_SURF_MACRO_TILE_ASPECT_8; break;
+        }
+}
+
 void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev)
 {
         u16 ctl, v;
@@ -68,6 +99,25 @@ void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev)
         }
 }
 
+void dce4_wait_for_vblank(struct radeon_device *rdev, int crtc)
+{
+        struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc];
+        int i;
+
+        if (RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset) & EVERGREEN_CRTC_MASTER_EN) {
+                for (i = 0; i < rdev->usec_timeout; i++) {
+                        if (!(RREG32(EVERGREEN_CRTC_STATUS + radeon_crtc->crtc_offset) & EVERGREEN_CRTC_V_BLANK))
+                                break;
+                        udelay(1);
+                }
+                for (i = 0; i < rdev->usec_timeout; i++) {
+                        if (RREG32(EVERGREEN_CRTC_STATUS + radeon_crtc->crtc_offset) & EVERGREEN_CRTC_V_BLANK)
+                                break;
+                        udelay(1);
+                }
+        }
+}
+
 void evergreen_pre_page_flip(struct radeon_device *rdev, int crtc)
 {
         /* enable the pflip int */
@@ -531,7 +581,7 @@ static u32 evergreen_line_buffer_adjust(struct radeon_device *rdev,
         return 0;
 }
 
-static u32 evergreen_get_number_of_dram_channels(struct radeon_device *rdev)
+u32 evergreen_get_number_of_dram_channels(struct radeon_device *rdev)
 {
         u32 tmp = RREG32(MC_SHARED_CHMAP);
 
@@ -1278,7 +1328,10 @@ void evergreen_mc_program(struct radeon_device *rdev)
                         rdev->mc.vram_end >> 12);
         }
         WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, rdev->vram_scratch.gpu_addr >> 12);
-        if (rdev->flags & RADEON_IS_IGP) {
+        /* llano/ontario only */
+        if ((rdev->family == CHIP_PALM) ||
+            (rdev->family == CHIP_SUMO) ||
+            (rdev->family == CHIP_SUMO2)) {
                 tmp = RREG32(MC_FUS_VM_FB_OFFSET) & 0x000FFFFF;
                 tmp |= ((rdev->mc.vram_end >> 20) & 0xF) << 24;
                 tmp |= ((rdev->mc.vram_start >> 20) & 0xF) << 20;
@@ -1489,7 +1542,7 @@ int evergreen_cp_resume(struct radeon_device *rdev)
 
         evergreen_cp_start(rdev);
         ring->ready = true;
-        r = radeon_ring_test(rdev, ring);
+        r = radeon_ring_test(rdev, RADEON_RING_TYPE_GFX_INDEX, ring);
         if (r) {
                 ring->ready = false;
                 return r;
@@ -1922,7 +1975,9 @@ static void evergreen_gpu_init(struct radeon_device *rdev)
 
 
         mc_shared_chmap = RREG32(MC_SHARED_CHMAP);
-        if (rdev->flags & RADEON_IS_IGP)
+        if ((rdev->family == CHIP_PALM) ||
+            (rdev->family == CHIP_SUMO) ||
+            (rdev->family == CHIP_SUMO2))
                 mc_arb_ramcfg = RREG32(FUS_MC_ARB_RAMCFG);
         else
                 mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
@@ -2312,7 +2367,9 @@ int evergreen_mc_init(struct radeon_device *rdev)
 
         /* Get VRAM informations */
         rdev->mc.vram_is_ddr = true;
-        if (rdev->flags & RADEON_IS_IGP)
+        if ((rdev->family == CHIP_PALM) ||
+            (rdev->family == CHIP_SUMO) ||
+            (rdev->family == CHIP_SUMO2))
                 tmp = RREG32(FUS_MC_ARB_RAMCFG);
         else
                 tmp = RREG32(MC_ARB_RAMCFG);
@@ -2344,12 +2401,14 @@ int evergreen_mc_init(struct radeon_device *rdev)
         rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
         rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
         /* Setup GPU memory space */
-        if (rdev->flags & RADEON_IS_IGP) {
+        if ((rdev->family == CHIP_PALM) ||
+            (rdev->family == CHIP_SUMO) ||
+            (rdev->family == CHIP_SUMO2)) {
                 /* size in bytes on fusion */
                 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
                 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
         } else {
-                /* size in MB on evergreen */
+                /* size in MB on evergreen/cayman/tn */
                 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
                 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
         }
@@ -2507,7 +2566,9 @@ void evergreen_disable_interrupt_state(struct radeon_device *rdev)
                 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
         }
 
-        WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
+        /* only one DAC on DCE6 */
+        if (!ASIC_IS_DCE6(rdev))
+                WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
         WREG32(DACB_AUTODETECT_INT_CONTROL, 0);
 
         tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
@@ -3147,7 +3208,7 @@ static int evergreen_startup(struct radeon_device *rdev)
         r = evergreen_blit_init(rdev);
         if (r) {
                 r600_blit_fini(rdev);
-                rdev->asic->copy = NULL;
+                rdev->asic->copy.copy = NULL;
                 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
         }
 
@@ -3187,7 +3248,7 @@ static int evergreen_startup(struct radeon_device *rdev)
         if (r)
                 return r;
 
-        r = r600_ib_test(rdev, RADEON_RING_TYPE_GFX_INDEX);
+        r = radeon_ib_test(rdev, RADEON_RING_TYPE_GFX_INDEX, &rdev->ring[RADEON_RING_TYPE_GFX_INDEX]);
         if (r) {
                 DRM_ERROR("radeon: failed testing IB (%d).\n", r);
                 rdev->accel_working = false;