diff options
Diffstat (limited to 'drivers/gpu/drm/radeon/evergreen.c')
| -rw-r--r-- | drivers/gpu/drm/radeon/evergreen.c | 28 |
1 files changed, 21 insertions, 7 deletions
diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c index 0318230ef274..653eff814504 100644 --- a/drivers/gpu/drm/radeon/evergreen.c +++ b/drivers/gpu/drm/radeon/evergreen.c | |||
| @@ -4355,7 +4355,6 @@ int evergreen_irq_set(struct radeon_device *rdev) | |||
| 4355 | u32 crtc1 = 0, crtc2 = 0, crtc3 = 0, crtc4 = 0, crtc5 = 0, crtc6 = 0; | 4355 | u32 crtc1 = 0, crtc2 = 0, crtc3 = 0, crtc4 = 0, crtc5 = 0, crtc6 = 0; |
| 4356 | u32 hpd1, hpd2, hpd3, hpd4, hpd5, hpd6; | 4356 | u32 hpd1, hpd2, hpd3, hpd4, hpd5, hpd6; |
| 4357 | u32 grbm_int_cntl = 0; | 4357 | u32 grbm_int_cntl = 0; |
| 4358 | u32 grph1 = 0, grph2 = 0, grph3 = 0, grph4 = 0, grph5 = 0, grph6 = 0; | ||
| 4359 | u32 afmt1 = 0, afmt2 = 0, afmt3 = 0, afmt4 = 0, afmt5 = 0, afmt6 = 0; | 4358 | u32 afmt1 = 0, afmt2 = 0, afmt3 = 0, afmt4 = 0, afmt5 = 0, afmt6 = 0; |
| 4360 | u32 dma_cntl, dma_cntl1 = 0; | 4359 | u32 dma_cntl, dma_cntl1 = 0; |
| 4361 | u32 thermal_int = 0; | 4360 | u32 thermal_int = 0; |
| @@ -4538,15 +4537,21 @@ int evergreen_irq_set(struct radeon_device *rdev) | |||
| 4538 | WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6); | 4537 | WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6); |
| 4539 | } | 4538 | } |
| 4540 | 4539 | ||
| 4541 | WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, grph1); | 4540 | WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, |
| 4542 | WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, grph2); | 4541 | GRPH_PFLIP_INT_MASK); |
| 4542 | WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, | ||
| 4543 | GRPH_PFLIP_INT_MASK); | ||
| 4543 | if (rdev->num_crtc >= 4) { | 4544 | if (rdev->num_crtc >= 4) { |
| 4544 | WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, grph3); | 4545 | WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, |
| 4545 | WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, grph4); | 4546 | GRPH_PFLIP_INT_MASK); |
| 4547 | WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, | ||
| 4548 | GRPH_PFLIP_INT_MASK); | ||
| 4546 | } | 4549 | } |
| 4547 | if (rdev->num_crtc >= 6) { | 4550 | if (rdev->num_crtc >= 6) { |
| 4548 | WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, grph5); | 4551 | WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, |
| 4549 | WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, grph6); | 4552 | GRPH_PFLIP_INT_MASK); |
| 4553 | WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, | ||
| 4554 | GRPH_PFLIP_INT_MASK); | ||
| 4550 | } | 4555 | } |
| 4551 | 4556 | ||
| 4552 | WREG32(DC_HPD1_INT_CONTROL, hpd1); | 4557 | WREG32(DC_HPD1_INT_CONTROL, hpd1); |
| @@ -4935,6 +4940,15 @@ restart_ih: | |||
| 4935 | break; | 4940 | break; |
| 4936 | } | 4941 | } |
| 4937 | break; | 4942 | break; |
| 4943 | case 8: /* D1 page flip */ | ||
| 4944 | case 10: /* D2 page flip */ | ||
| 4945 | case 12: /* D3 page flip */ | ||
| 4946 | case 14: /* D4 page flip */ | ||
| 4947 | case 16: /* D5 page flip */ | ||
| 4948 | case 18: /* D6 page flip */ | ||
| 4949 | DRM_DEBUG("IH: D%d flip\n", ((src_id - 8) >> 1) + 1); | ||
| 4950 | radeon_crtc_handle_flip(rdev, (src_id - 8) >> 1); | ||
| 4951 | break; | ||
| 4938 | case 42: /* HPD hotplug */ | 4952 | case 42: /* HPD hotplug */ |
| 4939 | switch (src_data) { | 4953 | switch (src_data) { |
| 4940 | case 0: | 4954 | case 0: |