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path: root/drivers/gpu/drm/radeon/evergreen.c
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Diffstat (limited to 'drivers/gpu/drm/radeon/evergreen.c')
-rw-r--r--drivers/gpu/drm/radeon/evergreen.c22
1 files changed, 10 insertions, 12 deletions
diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
index 98ea597bc76d..7162b7bacac0 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -88,7 +88,8 @@ u32 evergreen_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base)
88/* get temperature in millidegrees */ 88/* get temperature in millidegrees */
89int evergreen_get_temp(struct radeon_device *rdev) 89int evergreen_get_temp(struct radeon_device *rdev)
90{ 90{
91 u32 temp, toffset, actual_temp = 0; 91 u32 temp, toffset;
92 int actual_temp = 0;
92 93
93 if (rdev->family == CHIP_JUNIPER) { 94 if (rdev->family == CHIP_JUNIPER) {
94 toffset = (RREG32(CG_THERMAL_CTRL) & TOFFSET_MASK) >> 95 toffset = (RREG32(CG_THERMAL_CTRL) & TOFFSET_MASK) >>
@@ -2694,28 +2695,25 @@ static inline u32 evergreen_get_ih_wptr(struct radeon_device *rdev)
2694 2695
2695int evergreen_irq_process(struct radeon_device *rdev) 2696int evergreen_irq_process(struct radeon_device *rdev)
2696{ 2697{
2697 u32 wptr = evergreen_get_ih_wptr(rdev); 2698 u32 wptr;
2698 u32 rptr = rdev->ih.rptr; 2699 u32 rptr;
2699 u32 src_id, src_data; 2700 u32 src_id, src_data;
2700 u32 ring_index; 2701 u32 ring_index;
2701 unsigned long flags; 2702 unsigned long flags;
2702 bool queue_hotplug = false; 2703 bool queue_hotplug = false;
2703 2704
2704 DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr); 2705 if (!rdev->ih.enabled || rdev->shutdown)
2705 if (!rdev->ih.enabled)
2706 return IRQ_NONE; 2706 return IRQ_NONE;
2707 2707
2708 spin_lock_irqsave(&rdev->ih.lock, flags); 2708 wptr = evergreen_get_ih_wptr(rdev);
2709 rptr = rdev->ih.rptr;
2710 DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
2709 2711
2712 spin_lock_irqsave(&rdev->ih.lock, flags);
2710 if (rptr == wptr) { 2713 if (rptr == wptr) {
2711 spin_unlock_irqrestore(&rdev->ih.lock, flags); 2714 spin_unlock_irqrestore(&rdev->ih.lock, flags);
2712 return IRQ_NONE; 2715 return IRQ_NONE;
2713 } 2716 }
2714 if (rdev->shutdown) {
2715 spin_unlock_irqrestore(&rdev->ih.lock, flags);
2716 return IRQ_NONE;
2717 }
2718
2719restart_ih: 2717restart_ih:
2720 /* display interrupts */ 2718 /* display interrupts */
2721 evergreen_irq_ack(rdev); 2719 evergreen_irq_ack(rdev);
@@ -2944,7 +2942,7 @@ restart_ih:
2944 radeon_fence_process(rdev); 2942 radeon_fence_process(rdev);
2945 break; 2943 break;
2946 case 233: /* GUI IDLE */ 2944 case 233: /* GUI IDLE */
2947 DRM_DEBUG("IH: CP EOP\n"); 2945 DRM_DEBUG("IH: GUI idle\n");
2948 rdev->pm.gui_idle = true; 2946 rdev->pm.gui_idle = true;
2949 wake_up(&rdev->irq.idle_queue); 2947 wake_up(&rdev->irq.idle_queue);
2950 break; 2948 break;