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path: root/drivers/gpu/drm/radeon/evergreen.c
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Diffstat (limited to 'drivers/gpu/drm/radeon/evergreen.c')
-rw-r--r--drivers/gpu/drm/radeon/evergreen.c22
1 files changed, 17 insertions, 5 deletions
diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
index ffdc8332b76e..d270b3ff896b 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -1192,7 +1192,11 @@ void evergreen_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
1192 radeon_ring_write(rdev, 1); 1192 radeon_ring_write(rdev, 1);
1193 /* FIXME: implement */ 1193 /* FIXME: implement */
1194 radeon_ring_write(rdev, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 1194 radeon_ring_write(rdev, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
1195 radeon_ring_write(rdev, ib->gpu_addr & 0xFFFFFFFC); 1195 radeon_ring_write(rdev,
1196#ifdef __BIG_ENDIAN
1197 (2 << 0) |
1198#endif
1199 (ib->gpu_addr & 0xFFFFFFFC));
1196 radeon_ring_write(rdev, upper_32_bits(ib->gpu_addr) & 0xFF); 1200 radeon_ring_write(rdev, upper_32_bits(ib->gpu_addr) & 0xFF);
1197 radeon_ring_write(rdev, ib->length_dw); 1201 radeon_ring_write(rdev, ib->length_dw);
1198} 1202}
@@ -1207,7 +1211,11 @@ static int evergreen_cp_load_microcode(struct radeon_device *rdev)
1207 return -EINVAL; 1211 return -EINVAL;
1208 1212
1209 r700_cp_stop(rdev); 1213 r700_cp_stop(rdev);
1210 WREG32(CP_RB_CNTL, RB_NO_UPDATE | (15 << 8) | (3 << 0)); 1214 WREG32(CP_RB_CNTL,
1215#ifdef __BIG_ENDIAN
1216 BUF_SWAP_32BIT |
1217#endif
1218 RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3));
1211 1219
1212 fw_data = (const __be32 *)rdev->pfp_fw->data; 1220 fw_data = (const __be32 *)rdev->pfp_fw->data;
1213 WREG32(CP_PFP_UCODE_ADDR, 0); 1221 WREG32(CP_PFP_UCODE_ADDR, 0);
@@ -1326,7 +1334,11 @@ int evergreen_cp_resume(struct radeon_device *rdev)
1326 WREG32(CP_RB_WPTR, 0); 1334 WREG32(CP_RB_WPTR, 0);
1327 1335
1328 /* set the wb address wether it's enabled or not */ 1336 /* set the wb address wether it's enabled or not */
1329 WREG32(CP_RB_RPTR_ADDR, (rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC); 1337 WREG32(CP_RB_RPTR_ADDR,
1338#ifdef __BIG_ENDIAN
1339 RB_RPTR_SWAP(2) |
1340#endif
1341 ((rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFFFFFFFC));
1330 WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF); 1342 WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + RADEON_WB_CP_RPTR_OFFSET) & 0xFF);
1331 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF); 1343 WREG32(SCRATCH_ADDR, ((rdev->wb.gpu_addr + RADEON_WB_SCRATCH_OFFSET) >> 8) & 0xFFFFFFFF);
1332 1344
@@ -2627,8 +2639,8 @@ restart_ih:
2627 while (rptr != wptr) { 2639 while (rptr != wptr) {
2628 /* wptr/rptr are in bytes! */ 2640 /* wptr/rptr are in bytes! */
2629 ring_index = rptr / 4; 2641 ring_index = rptr / 4;
2630 src_id = rdev->ih.ring[ring_index] & 0xff; 2642 src_id = le32_to_cpu(rdev->ih.ring[ring_index]) & 0xff;
2631 src_data = rdev->ih.ring[ring_index + 1] & 0xfffffff; 2643 src_data = le32_to_cpu(rdev->ih.ring[ring_index + 1]) & 0xfffffff;
2632 2644
2633 switch (src_id) { 2645 switch (src_id) {
2634 case 1: /* D1 vblank/vline */ 2646 case 1: /* D1 vblank/vline */