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path: root/drivers/gpu/drm/radeon/evergreen.c
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Diffstat (limited to 'drivers/gpu/drm/radeon/evergreen.c')
-rw-r--r--drivers/gpu/drm/radeon/evergreen.c35
1 files changed, 29 insertions, 6 deletions
diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
index 4b6623df3b96..1caf625e472b 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -607,7 +607,7 @@ static void evergreen_mc_program(struct radeon_device *rdev)
607 WREG32(MC_VM_FB_LOCATION, tmp); 607 WREG32(MC_VM_FB_LOCATION, tmp);
608 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8)); 608 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
609 WREG32(HDP_NONSURFACE_INFO, (2 << 7)); 609 WREG32(HDP_NONSURFACE_INFO, (2 << 7));
610 WREG32(HDP_NONSURFACE_SIZE, (rdev->mc.mc_vram_size - 1) | 0x3FF); 610 WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
611 if (rdev->flags & RADEON_IS_AGP) { 611 if (rdev->flags & RADEON_IS_AGP) {
612 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16); 612 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16);
613 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16); 613 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16);
@@ -1222,11 +1222,11 @@ static void evergreen_gpu_init(struct radeon_device *rdev)
1222 ps_thread_count = 128; 1222 ps_thread_count = 128;
1223 1223
1224 sq_thread_resource_mgmt = NUM_PS_THREADS(ps_thread_count); 1224 sq_thread_resource_mgmt = NUM_PS_THREADS(ps_thread_count);
1225 sq_thread_resource_mgmt |= NUM_VS_THREADS(((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8; 1225 sq_thread_resource_mgmt |= NUM_VS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
1226 sq_thread_resource_mgmt |= NUM_GS_THREADS(((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8; 1226 sq_thread_resource_mgmt |= NUM_GS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
1227 sq_thread_resource_mgmt |= NUM_ES_THREADS(((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8; 1227 sq_thread_resource_mgmt |= NUM_ES_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
1228 sq_thread_resource_mgmt_2 = NUM_HS_THREADS(((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8; 1228 sq_thread_resource_mgmt_2 = NUM_HS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
1229 sq_thread_resource_mgmt_2 |= NUM_LS_THREADS(((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8; 1229 sq_thread_resource_mgmt_2 |= NUM_LS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
1230 1230
1231 sq_stack_resource_mgmt_1 = NUM_PS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6); 1231 sq_stack_resource_mgmt_1 = NUM_PS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
1232 sq_stack_resource_mgmt_1 |= NUM_VS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6); 1232 sq_stack_resource_mgmt_1 |= NUM_VS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
@@ -1260,6 +1260,9 @@ static void evergreen_gpu_init(struct radeon_device *rdev)
1260 WREG32(VGT_GS_VERTEX_REUSE, 16); 1260 WREG32(VGT_GS_VERTEX_REUSE, 16);
1261 WREG32(PA_SC_LINE_STIPPLE_STATE, 0); 1261 WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
1262 1262
1263 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, 14);
1264 WREG32(VGT_OUT_DEALLOC_CNTL, 16);
1265
1263 WREG32(CB_PERF_CTR0_SEL_0, 0); 1266 WREG32(CB_PERF_CTR0_SEL_0, 0);
1264 WREG32(CB_PERF_CTR0_SEL_1, 0); 1267 WREG32(CB_PERF_CTR0_SEL_1, 0);
1265 WREG32(CB_PERF_CTR1_SEL_0, 0); 1268 WREG32(CB_PERF_CTR1_SEL_0, 0);
@@ -1269,6 +1272,26 @@ static void evergreen_gpu_init(struct radeon_device *rdev)
1269 WREG32(CB_PERF_CTR3_SEL_0, 0); 1272 WREG32(CB_PERF_CTR3_SEL_0, 0);
1270 WREG32(CB_PERF_CTR3_SEL_1, 0); 1273 WREG32(CB_PERF_CTR3_SEL_1, 0);
1271 1274
1275 /* clear render buffer base addresses */
1276 WREG32(CB_COLOR0_BASE, 0);
1277 WREG32(CB_COLOR1_BASE, 0);
1278 WREG32(CB_COLOR2_BASE, 0);
1279 WREG32(CB_COLOR3_BASE, 0);
1280 WREG32(CB_COLOR4_BASE, 0);
1281 WREG32(CB_COLOR5_BASE, 0);
1282 WREG32(CB_COLOR6_BASE, 0);
1283 WREG32(CB_COLOR7_BASE, 0);
1284 WREG32(CB_COLOR8_BASE, 0);
1285 WREG32(CB_COLOR9_BASE, 0);
1286 WREG32(CB_COLOR10_BASE, 0);
1287 WREG32(CB_COLOR11_BASE, 0);
1288
1289 /* set the shader const cache sizes to 0 */
1290 for (i = SQ_ALU_CONST_BUFFER_SIZE_PS_0; i < 0x28200; i += 4)
1291 WREG32(i, 0);
1292 for (i = SQ_ALU_CONST_BUFFER_SIZE_HS_0; i < 0x29000; i += 4)
1293 WREG32(i, 0);
1294
1272 hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL); 1295 hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
1273 WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl); 1296 WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
1274 1297