diff options
Diffstat (limited to 'drivers/gpu/drm/radeon/evergreen.c')
-rw-r--r-- | drivers/gpu/drm/radeon/evergreen.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c index 78600f534c80..4c0e24b3bb90 100644 --- a/drivers/gpu/drm/radeon/evergreen.c +++ b/drivers/gpu/drm/radeon/evergreen.c | |||
@@ -3253,6 +3253,8 @@ static void evergreen_gpu_init(struct radeon_device *rdev) | |||
3253 | } | 3253 | } |
3254 | 3254 | ||
3255 | WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff)); | 3255 | WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff)); |
3256 | WREG32(SRBM_INT_CNTL, 0x1); | ||
3257 | WREG32(SRBM_INT_ACK, 0x1); | ||
3256 | 3258 | ||
3257 | evergreen_fix_pci_max_read_req_size(rdev); | 3259 | evergreen_fix_pci_max_read_req_size(rdev); |
3258 | 3260 | ||
@@ -4324,6 +4326,7 @@ void evergreen_disable_interrupt_state(struct radeon_device *rdev) | |||
4324 | tmp = RREG32(DMA_CNTL) & ~TRAP_ENABLE; | 4326 | tmp = RREG32(DMA_CNTL) & ~TRAP_ENABLE; |
4325 | WREG32(DMA_CNTL, tmp); | 4327 | WREG32(DMA_CNTL, tmp); |
4326 | WREG32(GRBM_INT_CNTL, 0); | 4328 | WREG32(GRBM_INT_CNTL, 0); |
4329 | WREG32(SRBM_INT_CNTL, 0); | ||
4327 | WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); | 4330 | WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); |
4328 | WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); | 4331 | WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); |
4329 | if (rdev->num_crtc >= 4) { | 4332 | if (rdev->num_crtc >= 4) { |
@@ -5066,6 +5069,10 @@ restart_ih: | |||
5066 | DRM_ERROR("Unhandled interrupt: %d %d\n", src_id, src_data); | 5069 | DRM_ERROR("Unhandled interrupt: %d %d\n", src_id, src_data); |
5067 | break; | 5070 | break; |
5068 | } | 5071 | } |
5072 | case 96: | ||
5073 | DRM_ERROR("SRBM_READ_ERROR: 0x%x\n", RREG32(SRBM_READ_ERROR)); | ||
5074 | WREG32(SRBM_INT_ACK, 0x1); | ||
5075 | break; | ||
5069 | case 124: /* UVD */ | 5076 | case 124: /* UVD */ |
5070 | DRM_DEBUG("IH: UVD int: 0x%08x\n", src_data); | 5077 | DRM_DEBUG("IH: UVD int: 0x%08x\n", src_data); |
5071 | radeon_fence_process(rdev, R600_RING_TYPE_UVD_INDEX); | 5078 | radeon_fence_process(rdev, R600_RING_TYPE_UVD_INDEX); |