diff options
Diffstat (limited to 'drivers/gpu/drm/radeon/evergreen.c')
| -rw-r--r-- | drivers/gpu/drm/radeon/evergreen.c | 28 |
1 files changed, 21 insertions, 7 deletions
diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c index b406546440da..0f7a51a3694f 100644 --- a/drivers/gpu/drm/radeon/evergreen.c +++ b/drivers/gpu/drm/radeon/evergreen.c | |||
| @@ -4371,7 +4371,6 @@ int evergreen_irq_set(struct radeon_device *rdev) | |||
| 4371 | u32 crtc1 = 0, crtc2 = 0, crtc3 = 0, crtc4 = 0, crtc5 = 0, crtc6 = 0; | 4371 | u32 crtc1 = 0, crtc2 = 0, crtc3 = 0, crtc4 = 0, crtc5 = 0, crtc6 = 0; |
| 4372 | u32 hpd1, hpd2, hpd3, hpd4, hpd5, hpd6; | 4372 | u32 hpd1, hpd2, hpd3, hpd4, hpd5, hpd6; |
| 4373 | u32 grbm_int_cntl = 0; | 4373 | u32 grbm_int_cntl = 0; |
| 4374 | u32 grph1 = 0, grph2 = 0, grph3 = 0, grph4 = 0, grph5 = 0, grph6 = 0; | ||
| 4375 | u32 afmt1 = 0, afmt2 = 0, afmt3 = 0, afmt4 = 0, afmt5 = 0, afmt6 = 0; | 4374 | u32 afmt1 = 0, afmt2 = 0, afmt3 = 0, afmt4 = 0, afmt5 = 0, afmt6 = 0; |
| 4376 | u32 dma_cntl, dma_cntl1 = 0; | 4375 | u32 dma_cntl, dma_cntl1 = 0; |
| 4377 | u32 thermal_int = 0; | 4376 | u32 thermal_int = 0; |
| @@ -4554,15 +4553,21 @@ int evergreen_irq_set(struct radeon_device *rdev) | |||
| 4554 | WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6); | 4553 | WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6); |
| 4555 | } | 4554 | } |
| 4556 | 4555 | ||
| 4557 | WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, grph1); | 4556 | WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, |
| 4558 | WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, grph2); | 4557 | GRPH_PFLIP_INT_MASK); |
| 4558 | WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, | ||
| 4559 | GRPH_PFLIP_INT_MASK); | ||
| 4559 | if (rdev->num_crtc >= 4) { | 4560 | if (rdev->num_crtc >= 4) { |
| 4560 | WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, grph3); | 4561 | WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, |
| 4561 | WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, grph4); | 4562 | GRPH_PFLIP_INT_MASK); |
| 4563 | WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, | ||
| 4564 | GRPH_PFLIP_INT_MASK); | ||
| 4562 | } | 4565 | } |
| 4563 | if (rdev->num_crtc >= 6) { | 4566 | if (rdev->num_crtc >= 6) { |
| 4564 | WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, grph5); | 4567 | WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, |
| 4565 | WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, grph6); | 4568 | GRPH_PFLIP_INT_MASK); |
| 4569 | WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, | ||
| 4570 | GRPH_PFLIP_INT_MASK); | ||
| 4566 | } | 4571 | } |
| 4567 | 4572 | ||
| 4568 | WREG32(DC_HPD1_INT_CONTROL, hpd1); | 4573 | WREG32(DC_HPD1_INT_CONTROL, hpd1); |
| @@ -4951,6 +4956,15 @@ restart_ih: | |||
| 4951 | break; | 4956 | break; |
| 4952 | } | 4957 | } |
| 4953 | break; | 4958 | break; |
| 4959 | case 8: /* D1 page flip */ | ||
| 4960 | case 10: /* D2 page flip */ | ||
| 4961 | case 12: /* D3 page flip */ | ||
| 4962 | case 14: /* D4 page flip */ | ||
| 4963 | case 16: /* D5 page flip */ | ||
| 4964 | case 18: /* D6 page flip */ | ||
| 4965 | DRM_DEBUG("IH: D%d flip\n", ((src_id - 8) >> 1) + 1); | ||
| 4966 | radeon_crtc_handle_flip(rdev, (src_id - 8) >> 1); | ||
| 4967 | break; | ||
| 4954 | case 42: /* HPD hotplug */ | 4968 | case 42: /* HPD hotplug */ |
| 4955 | switch (src_data) { | 4969 | switch (src_data) { |
| 4956 | case 0: | 4970 | case 0: |