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path: root/drivers/gpu/drm/radeon/evergreen.c
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Diffstat (limited to 'drivers/gpu/drm/radeon/evergreen.c')
-rw-r--r--drivers/gpu/drm/radeon/evergreen.c10
1 files changed, 3 insertions, 7 deletions
diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
index e585a3b947eb..b106c56c9af1 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -77,13 +77,9 @@ void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw,
77void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev) 77void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev)
78{ 78{
79 u16 ctl, v; 79 u16 ctl, v;
80 int cap, err; 80 int err;
81 81
82 cap = pci_pcie_cap(rdev->pdev); 82 err = pcie_capability_read_word(rdev->pdev, PCI_EXP_DEVCTL, &ctl);
83 if (!cap)
84 return;
85
86 err = pci_read_config_word(rdev->pdev, cap + PCI_EXP_DEVCTL, &ctl);
87 if (err) 83 if (err)
88 return; 84 return;
89 85
@@ -95,7 +91,7 @@ void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev)
95 if ((v == 0) || (v == 6) || (v == 7)) { 91 if ((v == 0) || (v == 6) || (v == 7)) {
96 ctl &= ~PCI_EXP_DEVCTL_READRQ; 92 ctl &= ~PCI_EXP_DEVCTL_READRQ;
97 ctl |= (2 << 12); 93 ctl |= (2 << 12);
98 pci_write_config_word(rdev->pdev, cap + PCI_EXP_DEVCTL, ctl); 94 pcie_capability_write_word(rdev->pdev, PCI_EXP_DEVCTL, ctl);
99 } 95 }
100} 96}
101 97