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path: root/drivers/gpu/drm/radeon/evergreen.c
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Diffstat (limited to 'drivers/gpu/drm/radeon/evergreen.c')
-rw-r--r--drivers/gpu/drm/radeon/evergreen.c31
1 files changed, 19 insertions, 12 deletions
diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
index 105bafb6c29d..8f9e2d31b255 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -2343,11 +2343,13 @@ void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *sav
2343 u32 crtc_enabled, tmp, frame_count, blackout; 2343 u32 crtc_enabled, tmp, frame_count, blackout;
2344 int i, j; 2344 int i, j;
2345 2345
2346 save->vga_render_control = RREG32(VGA_RENDER_CONTROL); 2346 if (!ASIC_IS_NODCE(rdev)) {
2347 save->vga_hdp_control = RREG32(VGA_HDP_CONTROL); 2347 save->vga_render_control = RREG32(VGA_RENDER_CONTROL);
2348 save->vga_hdp_control = RREG32(VGA_HDP_CONTROL);
2348 2349
2349 /* disable VGA render */ 2350 /* disable VGA render */
2350 WREG32(VGA_RENDER_CONTROL, 0); 2351 WREG32(VGA_RENDER_CONTROL, 0);
2352 }
2351 /* blank the display controllers */ 2353 /* blank the display controllers */
2352 for (i = 0; i < rdev->num_crtc; i++) { 2354 for (i = 0; i < rdev->num_crtc; i++) {
2353 crtc_enabled = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]) & EVERGREEN_CRTC_MASTER_EN; 2355 crtc_enabled = RREG32(EVERGREEN_CRTC_CONTROL + crtc_offsets[i]) & EVERGREEN_CRTC_MASTER_EN;
@@ -2438,8 +2440,11 @@ void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *s
2438 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + crtc_offsets[i], 2440 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + crtc_offsets[i],
2439 (u32)rdev->mc.vram_start); 2441 (u32)rdev->mc.vram_start);
2440 } 2442 }
2441 WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(rdev->mc.vram_start)); 2443
2442 WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start); 2444 if (!ASIC_IS_NODCE(rdev)) {
2445 WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(rdev->mc.vram_start));
2446 WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start);
2447 }
2443 2448
2444 /* unlock regs and wait for update */ 2449 /* unlock regs and wait for update */
2445 for (i = 0; i < rdev->num_crtc; i++) { 2450 for (i = 0; i < rdev->num_crtc; i++) {
@@ -2499,10 +2504,12 @@ void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *s
2499 } 2504 }
2500 } 2505 }
2501 } 2506 }
2502 /* Unlock vga access */ 2507 if (!ASIC_IS_NODCE(rdev)) {
2503 WREG32(VGA_HDP_CONTROL, save->vga_hdp_control); 2508 /* Unlock vga access */
2504 mdelay(1); 2509 WREG32(VGA_HDP_CONTROL, save->vga_hdp_control);
2505 WREG32(VGA_RENDER_CONTROL, save->vga_render_control); 2510 mdelay(1);
2511 WREG32(VGA_RENDER_CONTROL, save->vga_render_control);
2512 }
2506} 2513}
2507 2514
2508void evergreen_mc_program(struct radeon_device *rdev) 2515void evergreen_mc_program(struct radeon_device *rdev)
@@ -3405,8 +3412,8 @@ int evergreen_mc_init(struct radeon_device *rdev)
3405 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE); 3412 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
3406 } else { 3413 } else {
3407 /* size in MB on evergreen/cayman/tn */ 3414 /* size in MB on evergreen/cayman/tn */
3408 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024; 3415 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024ULL * 1024ULL;
3409 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024; 3416 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024ULL * 1024ULL;
3410 } 3417 }
3411 rdev->mc.visible_vram_size = rdev->mc.aper_size; 3418 rdev->mc.visible_vram_size = rdev->mc.aper_size;
3412 r700_vram_gtt_location(rdev, &rdev->mc); 3419 r700_vram_gtt_location(rdev, &rdev->mc);