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path: root/drivers/gpu/drm/radeon/evergreen.c
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Diffstat (limited to 'drivers/gpu/drm/radeon/evergreen.c')
-rw-r--r--drivers/gpu/drm/radeon/evergreen.c71
1 files changed, 11 insertions, 60 deletions
diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
index e585a3b947eb..e93b80a6d4e9 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -1229,24 +1229,8 @@ void evergreen_agp_enable(struct radeon_device *rdev)
1229 1229
1230void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save) 1230void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save)
1231{ 1231{
1232 save->vga_control[0] = RREG32(D1VGA_CONTROL);
1233 save->vga_control[1] = RREG32(D2VGA_CONTROL);
1234 save->vga_render_control = RREG32(VGA_RENDER_CONTROL); 1232 save->vga_render_control = RREG32(VGA_RENDER_CONTROL);
1235 save->vga_hdp_control = RREG32(VGA_HDP_CONTROL); 1233 save->vga_hdp_control = RREG32(VGA_HDP_CONTROL);
1236 save->crtc_control[0] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET);
1237 save->crtc_control[1] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET);
1238 if (rdev->num_crtc >= 4) {
1239 save->vga_control[2] = RREG32(EVERGREEN_D3VGA_CONTROL);
1240 save->vga_control[3] = RREG32(EVERGREEN_D4VGA_CONTROL);
1241 save->crtc_control[2] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET);
1242 save->crtc_control[3] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET);
1243 }
1244 if (rdev->num_crtc >= 6) {
1245 save->vga_control[4] = RREG32(EVERGREEN_D5VGA_CONTROL);
1246 save->vga_control[5] = RREG32(EVERGREEN_D6VGA_CONTROL);
1247 save->crtc_control[4] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET);
1248 save->crtc_control[5] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
1249 }
1250 1234
1251 /* Stop all video */ 1235 /* Stop all video */
1252 WREG32(VGA_RENDER_CONTROL, 0); 1236 WREG32(VGA_RENDER_CONTROL, 0);
@@ -1357,47 +1341,6 @@ void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *s
1357 /* Unlock host access */ 1341 /* Unlock host access */
1358 WREG32(VGA_HDP_CONTROL, save->vga_hdp_control); 1342 WREG32(VGA_HDP_CONTROL, save->vga_hdp_control);
1359 mdelay(1); 1343 mdelay(1);
1360 /* Restore video state */
1361 WREG32(D1VGA_CONTROL, save->vga_control[0]);
1362 WREG32(D2VGA_CONTROL, save->vga_control[1]);
1363 if (rdev->num_crtc >= 4) {
1364 WREG32(EVERGREEN_D3VGA_CONTROL, save->vga_control[2]);
1365 WREG32(EVERGREEN_D4VGA_CONTROL, save->vga_control[3]);
1366 }
1367 if (rdev->num_crtc >= 6) {
1368 WREG32(EVERGREEN_D5VGA_CONTROL, save->vga_control[4]);
1369 WREG32(EVERGREEN_D6VGA_CONTROL, save->vga_control[5]);
1370 }
1371 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 1);
1372 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 1);
1373 if (rdev->num_crtc >= 4) {
1374 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 1);
1375 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 1);
1376 }
1377 if (rdev->num_crtc >= 6) {
1378 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 1);
1379 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 1);
1380 }
1381 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, save->crtc_control[0]);
1382 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, save->crtc_control[1]);
1383 if (rdev->num_crtc >= 4) {
1384 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, save->crtc_control[2]);
1385 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, save->crtc_control[3]);
1386 }
1387 if (rdev->num_crtc >= 6) {
1388 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, save->crtc_control[4]);
1389 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, save->crtc_control[5]);
1390 }
1391 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
1392 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
1393 if (rdev->num_crtc >= 4) {
1394 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
1395 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
1396 }
1397 if (rdev->num_crtc >= 6) {
1398 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
1399 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
1400 }
1401 WREG32(VGA_RENDER_CONTROL, save->vga_render_control); 1344 WREG32(VGA_RENDER_CONTROL, save->vga_render_control);
1402} 1345}
1403 1346
@@ -1986,10 +1929,18 @@ static void evergreen_gpu_init(struct radeon_device *rdev)
1986 if (rdev->flags & RADEON_IS_IGP) 1929 if (rdev->flags & RADEON_IS_IGP)
1987 rdev->config.evergreen.tile_config |= 1 << 4; 1930 rdev->config.evergreen.tile_config |= 1 << 4;
1988 else { 1931 else {
1989 if ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) 1932 switch ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) {
1990 rdev->config.evergreen.tile_config |= 1 << 4; 1933 case 0: /* four banks */
1991 else
1992 rdev->config.evergreen.tile_config |= 0 << 4; 1934 rdev->config.evergreen.tile_config |= 0 << 4;
1935 break;
1936 case 1: /* eight banks */
1937 rdev->config.evergreen.tile_config |= 1 << 4;
1938 break;
1939 case 2: /* sixteen banks */
1940 default:
1941 rdev->config.evergreen.tile_config |= 2 << 4;
1942 break;
1943 }
1993 } 1944 }
1994 rdev->config.evergreen.tile_config |= 0 << 8; 1945 rdev->config.evergreen.tile_config |= 0 << 8;
1995 rdev->config.evergreen.tile_config |= 1946 rdev->config.evergreen.tile_config |=