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path: root/drivers/gpu/drm/radeon/evergreen.c
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Diffstat (limited to 'drivers/gpu/drm/radeon/evergreen.c')
-rw-r--r--drivers/gpu/drm/radeon/evergreen.c38
1 files changed, 38 insertions, 0 deletions
diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
index 4dc5b4714c5a..728358e6b798 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -1382,6 +1382,42 @@ static u32 evergreen_get_tile_pipe_to_backend_map(struct radeon_device *rdev,
1382 return backend_map; 1382 return backend_map;
1383} 1383}
1384 1384
1385static void evergreen_program_channel_remap(struct radeon_device *rdev)
1386{
1387 u32 tcp_chan_steer_lo, tcp_chan_steer_hi, mc_shared_chremap, tmp;
1388
1389 tmp = RREG32(MC_SHARED_CHMAP);
1390 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
1391 case 0:
1392 case 1:
1393 case 2:
1394 case 3:
1395 default:
1396 /* default mapping */
1397 mc_shared_chremap = 0x00fac688;
1398 break;
1399 }
1400
1401 switch (rdev->family) {
1402 case CHIP_HEMLOCK:
1403 case CHIP_CYPRESS:
1404 tcp_chan_steer_lo = 0x54763210;
1405 tcp_chan_steer_hi = 0x0000ba98;
1406 break;
1407 case CHIP_JUNIPER:
1408 case CHIP_REDWOOD:
1409 case CHIP_CEDAR:
1410 default:
1411 tcp_chan_steer_lo = 0x76543210;
1412 tcp_chan_steer_hi = 0x0000ba98;
1413 break;
1414 }
1415
1416 WREG32(TCP_CHAN_STEER_LO, tcp_chan_steer_lo);
1417 WREG32(TCP_CHAN_STEER_HI, tcp_chan_steer_hi);
1418 WREG32(MC_SHARED_CHREMAP, mc_shared_chremap);
1419}
1420
1385static void evergreen_gpu_init(struct radeon_device *rdev) 1421static void evergreen_gpu_init(struct radeon_device *rdev)
1386{ 1422{
1387 u32 cc_rb_backend_disable = 0; 1423 u32 cc_rb_backend_disable = 0;
@@ -1685,6 +1721,8 @@ static void evergreen_gpu_init(struct radeon_device *rdev)
1685 WREG32(DMIF_ADDR_CONFIG, gb_addr_config); 1721 WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
1686 WREG32(HDP_ADDR_CONFIG, gb_addr_config); 1722 WREG32(HDP_ADDR_CONFIG, gb_addr_config);
1687 1723
1724 evergreen_program_channel_remap(rdev);
1725
1688 num_shader_engines = ((RREG32(GB_ADDR_CONFIG) & NUM_SHADER_ENGINES(3)) >> 12) + 1; 1726 num_shader_engines = ((RREG32(GB_ADDR_CONFIG) & NUM_SHADER_ENGINES(3)) >> 12) + 1;
1689 grbm_gfx_index = INSTANCE_BROADCAST_WRITES; 1727 grbm_gfx_index = INSTANCE_BROADCAST_WRITES;
1690 1728