diff options
Diffstat (limited to 'drivers/gpu/drm/radeon/evergreen.c')
-rw-r--r-- | drivers/gpu/drm/radeon/evergreen.c | 71 |
1 files changed, 11 insertions, 60 deletions
diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c index b106c56c9af1..ed3340adeb6f 100644 --- a/drivers/gpu/drm/radeon/evergreen.c +++ b/drivers/gpu/drm/radeon/evergreen.c | |||
@@ -1225,24 +1225,8 @@ void evergreen_agp_enable(struct radeon_device *rdev) | |||
1225 | 1225 | ||
1226 | void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save) | 1226 | void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save) |
1227 | { | 1227 | { |
1228 | save->vga_control[0] = RREG32(D1VGA_CONTROL); | ||
1229 | save->vga_control[1] = RREG32(D2VGA_CONTROL); | ||
1230 | save->vga_render_control = RREG32(VGA_RENDER_CONTROL); | 1228 | save->vga_render_control = RREG32(VGA_RENDER_CONTROL); |
1231 | save->vga_hdp_control = RREG32(VGA_HDP_CONTROL); | 1229 | save->vga_hdp_control = RREG32(VGA_HDP_CONTROL); |
1232 | save->crtc_control[0] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET); | ||
1233 | save->crtc_control[1] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET); | ||
1234 | if (rdev->num_crtc >= 4) { | ||
1235 | save->vga_control[2] = RREG32(EVERGREEN_D3VGA_CONTROL); | ||
1236 | save->vga_control[3] = RREG32(EVERGREEN_D4VGA_CONTROL); | ||
1237 | save->crtc_control[2] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET); | ||
1238 | save->crtc_control[3] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET); | ||
1239 | } | ||
1240 | if (rdev->num_crtc >= 6) { | ||
1241 | save->vga_control[4] = RREG32(EVERGREEN_D5VGA_CONTROL); | ||
1242 | save->vga_control[5] = RREG32(EVERGREEN_D6VGA_CONTROL); | ||
1243 | save->crtc_control[4] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET); | ||
1244 | save->crtc_control[5] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET); | ||
1245 | } | ||
1246 | 1230 | ||
1247 | /* Stop all video */ | 1231 | /* Stop all video */ |
1248 | WREG32(VGA_RENDER_CONTROL, 0); | 1232 | WREG32(VGA_RENDER_CONTROL, 0); |
@@ -1353,47 +1337,6 @@ void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *s | |||
1353 | /* Unlock host access */ | 1337 | /* Unlock host access */ |
1354 | WREG32(VGA_HDP_CONTROL, save->vga_hdp_control); | 1338 | WREG32(VGA_HDP_CONTROL, save->vga_hdp_control); |
1355 | mdelay(1); | 1339 | mdelay(1); |
1356 | /* Restore video state */ | ||
1357 | WREG32(D1VGA_CONTROL, save->vga_control[0]); | ||
1358 | WREG32(D2VGA_CONTROL, save->vga_control[1]); | ||
1359 | if (rdev->num_crtc >= 4) { | ||
1360 | WREG32(EVERGREEN_D3VGA_CONTROL, save->vga_control[2]); | ||
1361 | WREG32(EVERGREEN_D4VGA_CONTROL, save->vga_control[3]); | ||
1362 | } | ||
1363 | if (rdev->num_crtc >= 6) { | ||
1364 | WREG32(EVERGREEN_D5VGA_CONTROL, save->vga_control[4]); | ||
1365 | WREG32(EVERGREEN_D6VGA_CONTROL, save->vga_control[5]); | ||
1366 | } | ||
1367 | WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 1); | ||
1368 | WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 1); | ||
1369 | if (rdev->num_crtc >= 4) { | ||
1370 | WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 1); | ||
1371 | WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 1); | ||
1372 | } | ||
1373 | if (rdev->num_crtc >= 6) { | ||
1374 | WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 1); | ||
1375 | WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 1); | ||
1376 | } | ||
1377 | WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, save->crtc_control[0]); | ||
1378 | WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, save->crtc_control[1]); | ||
1379 | if (rdev->num_crtc >= 4) { | ||
1380 | WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, save->crtc_control[2]); | ||
1381 | WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, save->crtc_control[3]); | ||
1382 | } | ||
1383 | if (rdev->num_crtc >= 6) { | ||
1384 | WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, save->crtc_control[4]); | ||
1385 | WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, save->crtc_control[5]); | ||
1386 | } | ||
1387 | WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); | ||
1388 | WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); | ||
1389 | if (rdev->num_crtc >= 4) { | ||
1390 | WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0); | ||
1391 | WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0); | ||
1392 | } | ||
1393 | if (rdev->num_crtc >= 6) { | ||
1394 | WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0); | ||
1395 | WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0); | ||
1396 | } | ||
1397 | WREG32(VGA_RENDER_CONTROL, save->vga_render_control); | 1340 | WREG32(VGA_RENDER_CONTROL, save->vga_render_control); |
1398 | } | 1341 | } |
1399 | 1342 | ||
@@ -1982,10 +1925,18 @@ static void evergreen_gpu_init(struct radeon_device *rdev) | |||
1982 | if (rdev->flags & RADEON_IS_IGP) | 1925 | if (rdev->flags & RADEON_IS_IGP) |
1983 | rdev->config.evergreen.tile_config |= 1 << 4; | 1926 | rdev->config.evergreen.tile_config |= 1 << 4; |
1984 | else { | 1927 | else { |
1985 | if ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) | 1928 | switch ((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT) { |
1986 | rdev->config.evergreen.tile_config |= 1 << 4; | 1929 | case 0: /* four banks */ |
1987 | else | ||
1988 | rdev->config.evergreen.tile_config |= 0 << 4; | 1930 | rdev->config.evergreen.tile_config |= 0 << 4; |
1931 | break; | ||
1932 | case 1: /* eight banks */ | ||
1933 | rdev->config.evergreen.tile_config |= 1 << 4; | ||
1934 | break; | ||
1935 | case 2: /* sixteen banks */ | ||
1936 | default: | ||
1937 | rdev->config.evergreen.tile_config |= 2 << 4; | ||
1938 | break; | ||
1939 | } | ||
1989 | } | 1940 | } |
1990 | rdev->config.evergreen.tile_config |= 0 << 8; | 1941 | rdev->config.evergreen.tile_config |= 0 << 8; |
1991 | rdev->config.evergreen.tile_config |= | 1942 | rdev->config.evergreen.tile_config |= |