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path: root/drivers/gpu/drm/radeon/evergreen.c
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Diffstat (limited to 'drivers/gpu/drm/radeon/evergreen.c')
-rw-r--r--drivers/gpu/drm/radeon/evergreen.c806
1 files changed, 604 insertions, 202 deletions
diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
index 7b337c361a12..7fe8ebdcdc0e 100644
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -39,6 +39,62 @@
39 39
40static void evergreen_gpu_init(struct radeon_device *rdev); 40static void evergreen_gpu_init(struct radeon_device *rdev);
41void evergreen_fini(struct radeon_device *rdev); 41void evergreen_fini(struct radeon_device *rdev);
42static void evergreen_pcie_gen2_enable(struct radeon_device *rdev);
43
44void evergreen_pre_page_flip(struct radeon_device *rdev, int crtc)
45{
46 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc];
47 u32 tmp;
48
49 /* make sure flip is at vb rather than hb */
50 tmp = RREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset);
51 tmp &= ~EVERGREEN_GRPH_SURFACE_UPDATE_H_RETRACE_EN;
52 WREG32(EVERGREEN_GRPH_FLIP_CONTROL + radeon_crtc->crtc_offset, tmp);
53
54 /* set pageflip to happen anywhere in vblank interval */
55 WREG32(EVERGREEN_MASTER_UPDATE_MODE + radeon_crtc->crtc_offset, 0);
56
57 /* enable the pflip int */
58 radeon_irq_kms_pflip_irq_get(rdev, crtc);
59}
60
61void evergreen_post_page_flip(struct radeon_device *rdev, int crtc)
62{
63 /* disable the pflip int */
64 radeon_irq_kms_pflip_irq_put(rdev, crtc);
65}
66
67u32 evergreen_page_flip(struct radeon_device *rdev, int crtc_id, u64 crtc_base)
68{
69 struct radeon_crtc *radeon_crtc = rdev->mode_info.crtcs[crtc_id];
70 u32 tmp = RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset);
71
72 /* Lock the graphics update lock */
73 tmp |= EVERGREEN_GRPH_UPDATE_LOCK;
74 WREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
75
76 /* update the scanout addresses */
77 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
78 upper_32_bits(crtc_base));
79 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
80 (u32)crtc_base);
81
82 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
83 upper_32_bits(crtc_base));
84 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
85 (u32)crtc_base);
86
87 /* Wait for update_pending to go high. */
88 while (!(RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset) & EVERGREEN_GRPH_SURFACE_UPDATE_PENDING));
89 DRM_DEBUG("Update pending now high. Unlocking vupdate_lock.\n");
90
91 /* Unlock the lock, so double-buffering can take place inside vblank */
92 tmp &= ~EVERGREEN_GRPH_UPDATE_LOCK;
93 WREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset, tmp);
94
95 /* Return current update_pending status: */
96 return RREG32(EVERGREEN_GRPH_UPDATE + radeon_crtc->crtc_offset) & EVERGREEN_GRPH_SURFACE_UPDATE_PENDING;
97}
42 98
43/* get temperature in millidegrees */ 99/* get temperature in millidegrees */
44u32 evergreen_get_temp(struct radeon_device *rdev) 100u32 evergreen_get_temp(struct radeon_device *rdev)
@@ -57,6 +113,14 @@ u32 evergreen_get_temp(struct radeon_device *rdev)
57 return actual_temp * 1000; 113 return actual_temp * 1000;
58} 114}
59 115
116u32 sumo_get_temp(struct radeon_device *rdev)
117{
118 u32 temp = RREG32(CG_THERMAL_STATUS) & 0xff;
119 u32 actual_temp = (temp >> 1) & 0xff;
120
121 return actual_temp * 1000;
122}
123
60void evergreen_pm_misc(struct radeon_device *rdev) 124void evergreen_pm_misc(struct radeon_device *rdev)
61{ 125{
62 int req_ps_idx = rdev->pm.requested_power_state_index; 126 int req_ps_idx = rdev->pm.requested_power_state_index;
@@ -337,16 +401,28 @@ static u32 evergreen_line_buffer_adjust(struct radeon_device *rdev,
337 case 0: 401 case 0:
338 case 4: 402 case 4:
339 default: 403 default:
340 return 3840 * 2; 404 if (ASIC_IS_DCE5(rdev))
405 return 4096 * 2;
406 else
407 return 3840 * 2;
341 case 1: 408 case 1:
342 case 5: 409 case 5:
343 return 5760 * 2; 410 if (ASIC_IS_DCE5(rdev))
411 return 6144 * 2;
412 else
413 return 5760 * 2;
344 case 2: 414 case 2:
345 case 6: 415 case 6:
346 return 7680 * 2; 416 if (ASIC_IS_DCE5(rdev))
417 return 8192 * 2;
418 else
419 return 7680 * 2;
347 case 3: 420 case 3:
348 case 7: 421 case 7:
349 return 1920 * 2; 422 if (ASIC_IS_DCE5(rdev))
423 return 2048 * 2;
424 else
425 return 1920 * 2;
350 } 426 }
351} 427}
352 428
@@ -890,31 +966,39 @@ static void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_sa
890 save->vga_hdp_control = RREG32(VGA_HDP_CONTROL); 966 save->vga_hdp_control = RREG32(VGA_HDP_CONTROL);
891 save->crtc_control[0] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET); 967 save->crtc_control[0] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET);
892 save->crtc_control[1] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET); 968 save->crtc_control[1] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET);
893 save->crtc_control[2] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET); 969 if (!(rdev->flags & RADEON_IS_IGP)) {
894 save->crtc_control[3] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET); 970 save->crtc_control[2] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET);
895 save->crtc_control[4] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET); 971 save->crtc_control[3] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET);
896 save->crtc_control[5] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET); 972 save->crtc_control[4] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET);
973 save->crtc_control[5] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
974 }
897 975
898 /* Stop all video */ 976 /* Stop all video */
899 WREG32(VGA_RENDER_CONTROL, 0); 977 WREG32(VGA_RENDER_CONTROL, 0);
900 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 1); 978 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 1);
901 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 1); 979 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 1);
902 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 1); 980 if (!(rdev->flags & RADEON_IS_IGP)) {
903 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 1); 981 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 1);
904 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 1); 982 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 1);
905 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 1); 983 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 1);
984 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 1);
985 }
906 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); 986 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
907 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); 987 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
908 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0); 988 if (!(rdev->flags & RADEON_IS_IGP)) {
909 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0); 989 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
910 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0); 990 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
911 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0); 991 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
992 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
993 }
912 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); 994 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
913 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); 995 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
914 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0); 996 if (!(rdev->flags & RADEON_IS_IGP)) {
915 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0); 997 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
916 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0); 998 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
917 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0); 999 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
1000 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
1001 }
918 1002
919 WREG32(D1VGA_CONTROL, 0); 1003 WREG32(D1VGA_CONTROL, 0);
920 WREG32(D2VGA_CONTROL, 0); 1004 WREG32(D2VGA_CONTROL, 0);
@@ -944,41 +1028,43 @@ static void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_
944 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC1_REGISTER_OFFSET, 1028 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC1_REGISTER_OFFSET,
945 (u32)rdev->mc.vram_start); 1029 (u32)rdev->mc.vram_start);
946 1030
947 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC2_REGISTER_OFFSET, 1031 if (!(rdev->flags & RADEON_IS_IGP)) {
948 upper_32_bits(rdev->mc.vram_start)); 1032 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC2_REGISTER_OFFSET,
949 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC2_REGISTER_OFFSET, 1033 upper_32_bits(rdev->mc.vram_start));
950 upper_32_bits(rdev->mc.vram_start)); 1034 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC2_REGISTER_OFFSET,
951 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC2_REGISTER_OFFSET, 1035 upper_32_bits(rdev->mc.vram_start));
952 (u32)rdev->mc.vram_start); 1036 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC2_REGISTER_OFFSET,
953 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC2_REGISTER_OFFSET, 1037 (u32)rdev->mc.vram_start);
954 (u32)rdev->mc.vram_start); 1038 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC2_REGISTER_OFFSET,
955 1039 (u32)rdev->mc.vram_start);
956 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC3_REGISTER_OFFSET, 1040
957 upper_32_bits(rdev->mc.vram_start)); 1041 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC3_REGISTER_OFFSET,
958 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC3_REGISTER_OFFSET, 1042 upper_32_bits(rdev->mc.vram_start));
959 upper_32_bits(rdev->mc.vram_start)); 1043 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC3_REGISTER_OFFSET,
960 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC3_REGISTER_OFFSET, 1044 upper_32_bits(rdev->mc.vram_start));
961 (u32)rdev->mc.vram_start); 1045 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC3_REGISTER_OFFSET,
962 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC3_REGISTER_OFFSET, 1046 (u32)rdev->mc.vram_start);
963 (u32)rdev->mc.vram_start); 1047 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC3_REGISTER_OFFSET,
964 1048 (u32)rdev->mc.vram_start);
965 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC4_REGISTER_OFFSET, 1049
966 upper_32_bits(rdev->mc.vram_start)); 1050 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC4_REGISTER_OFFSET,
967 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC4_REGISTER_OFFSET, 1051 upper_32_bits(rdev->mc.vram_start));
968 upper_32_bits(rdev->mc.vram_start)); 1052 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC4_REGISTER_OFFSET,
969 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC4_REGISTER_OFFSET, 1053 upper_32_bits(rdev->mc.vram_start));
970 (u32)rdev->mc.vram_start); 1054 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC4_REGISTER_OFFSET,
971 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC4_REGISTER_OFFSET, 1055 (u32)rdev->mc.vram_start);
972 (u32)rdev->mc.vram_start); 1056 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC4_REGISTER_OFFSET,
973 1057 (u32)rdev->mc.vram_start);
974 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC5_REGISTER_OFFSET, 1058
975 upper_32_bits(rdev->mc.vram_start)); 1059 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC5_REGISTER_OFFSET,
976 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC5_REGISTER_OFFSET, 1060 upper_32_bits(rdev->mc.vram_start));
977 upper_32_bits(rdev->mc.vram_start)); 1061 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC5_REGISTER_OFFSET,
978 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC5_REGISTER_OFFSET, 1062 upper_32_bits(rdev->mc.vram_start));
979 (u32)rdev->mc.vram_start); 1063 WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC5_REGISTER_OFFSET,
980 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC5_REGISTER_OFFSET, 1064 (u32)rdev->mc.vram_start);
981 (u32)rdev->mc.vram_start); 1065 WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC5_REGISTER_OFFSET,
1066 (u32)rdev->mc.vram_start);
1067 }
982 1068
983 WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(rdev->mc.vram_start)); 1069 WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(rdev->mc.vram_start));
984 WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start); 1070 WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start);
@@ -994,22 +1080,28 @@ static void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_
994 WREG32(EVERGREEN_D6VGA_CONTROL, save->vga_control[5]); 1080 WREG32(EVERGREEN_D6VGA_CONTROL, save->vga_control[5]);
995 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 1); 1081 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 1);
996 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 1); 1082 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 1);
997 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 1); 1083 if (!(rdev->flags & RADEON_IS_IGP)) {
998 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 1); 1084 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 1);
999 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 1); 1085 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 1);
1000 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 1); 1086 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 1);
1087 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 1);
1088 }
1001 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, save->crtc_control[0]); 1089 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, save->crtc_control[0]);
1002 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, save->crtc_control[1]); 1090 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, save->crtc_control[1]);
1003 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, save->crtc_control[2]); 1091 if (!(rdev->flags & RADEON_IS_IGP)) {
1004 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, save->crtc_control[3]); 1092 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, save->crtc_control[2]);
1005 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, save->crtc_control[4]); 1093 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, save->crtc_control[3]);
1006 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, save->crtc_control[5]); 1094 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, save->crtc_control[4]);
1095 WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, save->crtc_control[5]);
1096 }
1007 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); 1097 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
1008 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); 1098 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
1009 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0); 1099 if (!(rdev->flags & RADEON_IS_IGP)) {
1010 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0); 1100 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
1011 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0); 1101 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
1012 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0); 1102 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
1103 WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
1104 }
1013 WREG32(VGA_RENDER_CONTROL, save->vga_render_control); 1105 WREG32(VGA_RENDER_CONTROL, save->vga_render_control);
1014} 1106}
1015 1107
@@ -1057,11 +1149,17 @@ static void evergreen_mc_program(struct radeon_device *rdev)
1057 rdev->mc.vram_end >> 12); 1149 rdev->mc.vram_end >> 12);
1058 } 1150 }
1059 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0); 1151 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
1152 if (rdev->flags & RADEON_IS_IGP) {
1153 tmp = RREG32(MC_FUS_VM_FB_OFFSET) & 0x000FFFFF;
1154 tmp |= ((rdev->mc.vram_end >> 20) & 0xF) << 24;
1155 tmp |= ((rdev->mc.vram_start >> 20) & 0xF) << 20;
1156 WREG32(MC_FUS_VM_FB_OFFSET, tmp);
1157 }
1060 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16; 1158 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
1061 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF); 1159 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
1062 WREG32(MC_VM_FB_LOCATION, tmp); 1160 WREG32(MC_VM_FB_LOCATION, tmp);
1063 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8)); 1161 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
1064 WREG32(HDP_NONSURFACE_INFO, (2 << 7)); 1162 WREG32(HDP_NONSURFACE_INFO, (2 << 7) | (1 << 30));
1065 WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF); 1163 WREG32(HDP_NONSURFACE_SIZE, 0x3FFFFFFF);
1066 if (rdev->flags & RADEON_IS_AGP) { 1164 if (rdev->flags & RADEON_IS_AGP) {
1067 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16); 1165 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16);
@@ -1285,11 +1383,15 @@ static u32 evergreen_get_tile_pipe_to_backend_map(struct radeon_device *rdev,
1285 switch (rdev->family) { 1383 switch (rdev->family) {
1286 case CHIP_CEDAR: 1384 case CHIP_CEDAR:
1287 case CHIP_REDWOOD: 1385 case CHIP_REDWOOD:
1386 case CHIP_PALM:
1387 case CHIP_TURKS:
1388 case CHIP_CAICOS:
1288 force_no_swizzle = false; 1389 force_no_swizzle = false;
1289 break; 1390 break;
1290 case CHIP_CYPRESS: 1391 case CHIP_CYPRESS:
1291 case CHIP_HEMLOCK: 1392 case CHIP_HEMLOCK:
1292 case CHIP_JUNIPER: 1393 case CHIP_JUNIPER:
1394 case CHIP_BARTS:
1293 default: 1395 default:
1294 force_no_swizzle = true; 1396 force_no_swizzle = true;
1295 break; 1397 break;
@@ -1384,6 +1486,46 @@ static u32 evergreen_get_tile_pipe_to_backend_map(struct radeon_device *rdev,
1384 return backend_map; 1486 return backend_map;
1385} 1487}
1386 1488
1489static void evergreen_program_channel_remap(struct radeon_device *rdev)
1490{
1491 u32 tcp_chan_steer_lo, tcp_chan_steer_hi, mc_shared_chremap, tmp;
1492
1493 tmp = RREG32(MC_SHARED_CHMAP);
1494 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
1495 case 0:
1496 case 1:
1497 case 2:
1498 case 3:
1499 default:
1500 /* default mapping */
1501 mc_shared_chremap = 0x00fac688;
1502 break;
1503 }
1504
1505 switch (rdev->family) {
1506 case CHIP_HEMLOCK:
1507 case CHIP_CYPRESS:
1508 case CHIP_BARTS:
1509 tcp_chan_steer_lo = 0x54763210;
1510 tcp_chan_steer_hi = 0x0000ba98;
1511 break;
1512 case CHIP_JUNIPER:
1513 case CHIP_REDWOOD:
1514 case CHIP_CEDAR:
1515 case CHIP_PALM:
1516 case CHIP_TURKS:
1517 case CHIP_CAICOS:
1518 default:
1519 tcp_chan_steer_lo = 0x76543210;
1520 tcp_chan_steer_hi = 0x0000ba98;
1521 break;
1522 }
1523
1524 WREG32(TCP_CHAN_STEER_LO, tcp_chan_steer_lo);
1525 WREG32(TCP_CHAN_STEER_HI, tcp_chan_steer_hi);
1526 WREG32(MC_SHARED_CHREMAP, mc_shared_chremap);
1527}
1528
1387static void evergreen_gpu_init(struct radeon_device *rdev) 1529static void evergreen_gpu_init(struct radeon_device *rdev)
1388{ 1530{
1389 u32 cc_rb_backend_disable = 0; 1531 u32 cc_rb_backend_disable = 0;
@@ -1495,6 +1637,90 @@ static void evergreen_gpu_init(struct radeon_device *rdev)
1495 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30; 1637 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1496 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130; 1638 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1497 break; 1639 break;
1640 case CHIP_PALM:
1641 rdev->config.evergreen.num_ses = 1;
1642 rdev->config.evergreen.max_pipes = 2;
1643 rdev->config.evergreen.max_tile_pipes = 2;
1644 rdev->config.evergreen.max_simds = 2;
1645 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
1646 rdev->config.evergreen.max_gprs = 256;
1647 rdev->config.evergreen.max_threads = 192;
1648 rdev->config.evergreen.max_gs_threads = 16;
1649 rdev->config.evergreen.max_stack_entries = 256;
1650 rdev->config.evergreen.sx_num_of_sets = 4;
1651 rdev->config.evergreen.sx_max_export_size = 128;
1652 rdev->config.evergreen.sx_max_export_pos_size = 32;
1653 rdev->config.evergreen.sx_max_export_smx_size = 96;
1654 rdev->config.evergreen.max_hw_contexts = 4;
1655 rdev->config.evergreen.sq_num_cf_insts = 1;
1656
1657 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1658 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1659 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1660 break;
1661 case CHIP_BARTS:
1662 rdev->config.evergreen.num_ses = 2;
1663 rdev->config.evergreen.max_pipes = 4;
1664 rdev->config.evergreen.max_tile_pipes = 8;
1665 rdev->config.evergreen.max_simds = 7;
1666 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;
1667 rdev->config.evergreen.max_gprs = 256;
1668 rdev->config.evergreen.max_threads = 248;
1669 rdev->config.evergreen.max_gs_threads = 32;
1670 rdev->config.evergreen.max_stack_entries = 512;
1671 rdev->config.evergreen.sx_num_of_sets = 4;
1672 rdev->config.evergreen.sx_max_export_size = 256;
1673 rdev->config.evergreen.sx_max_export_pos_size = 64;
1674 rdev->config.evergreen.sx_max_export_smx_size = 192;
1675 rdev->config.evergreen.max_hw_contexts = 8;
1676 rdev->config.evergreen.sq_num_cf_insts = 2;
1677
1678 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1679 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1680 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1681 break;
1682 case CHIP_TURKS:
1683 rdev->config.evergreen.num_ses = 1;
1684 rdev->config.evergreen.max_pipes = 4;
1685 rdev->config.evergreen.max_tile_pipes = 4;
1686 rdev->config.evergreen.max_simds = 6;
1687 rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses;
1688 rdev->config.evergreen.max_gprs = 256;
1689 rdev->config.evergreen.max_threads = 248;
1690 rdev->config.evergreen.max_gs_threads = 32;
1691 rdev->config.evergreen.max_stack_entries = 256;
1692 rdev->config.evergreen.sx_num_of_sets = 4;
1693 rdev->config.evergreen.sx_max_export_size = 256;
1694 rdev->config.evergreen.sx_max_export_pos_size = 64;
1695 rdev->config.evergreen.sx_max_export_smx_size = 192;
1696 rdev->config.evergreen.max_hw_contexts = 8;
1697 rdev->config.evergreen.sq_num_cf_insts = 2;
1698
1699 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
1700 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1701 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1702 break;
1703 case CHIP_CAICOS:
1704 rdev->config.evergreen.num_ses = 1;
1705 rdev->config.evergreen.max_pipes = 4;
1706 rdev->config.evergreen.max_tile_pipes = 2;
1707 rdev->config.evergreen.max_simds = 2;
1708 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
1709 rdev->config.evergreen.max_gprs = 256;
1710 rdev->config.evergreen.max_threads = 192;
1711 rdev->config.evergreen.max_gs_threads = 16;
1712 rdev->config.evergreen.max_stack_entries = 256;
1713 rdev->config.evergreen.sx_num_of_sets = 4;
1714 rdev->config.evergreen.sx_max_export_size = 128;
1715 rdev->config.evergreen.sx_max_export_pos_size = 32;
1716 rdev->config.evergreen.sx_max_export_smx_size = 96;
1717 rdev->config.evergreen.max_hw_contexts = 4;
1718 rdev->config.evergreen.sq_num_cf_insts = 1;
1719
1720 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
1721 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
1722 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
1723 break;
1498 } 1724 }
1499 1725
1500 /* Initialize HDP */ 1726 /* Initialize HDP */
@@ -1636,6 +1862,7 @@ static void evergreen_gpu_init(struct radeon_device *rdev)
1636 switch (rdev->family) { 1862 switch (rdev->family) {
1637 case CHIP_CYPRESS: 1863 case CHIP_CYPRESS:
1638 case CHIP_HEMLOCK: 1864 case CHIP_HEMLOCK:
1865 case CHIP_BARTS:
1639 gb_backend_map = 0x66442200; 1866 gb_backend_map = 0x66442200;
1640 break; 1867 break;
1641 case CHIP_JUNIPER: 1868 case CHIP_JUNIPER:
@@ -1687,6 +1914,8 @@ static void evergreen_gpu_init(struct radeon_device *rdev)
1687 WREG32(DMIF_ADDR_CONFIG, gb_addr_config); 1914 WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
1688 WREG32(HDP_ADDR_CONFIG, gb_addr_config); 1915 WREG32(HDP_ADDR_CONFIG, gb_addr_config);
1689 1916
1917 evergreen_program_channel_remap(rdev);
1918
1690 num_shader_engines = ((RREG32(GB_ADDR_CONFIG) & NUM_SHADER_ENGINES(3)) >> 12) + 1; 1919 num_shader_engines = ((RREG32(GB_ADDR_CONFIG) & NUM_SHADER_ENGINES(3)) >> 12) + 1;
1691 grbm_gfx_index = INSTANCE_BROADCAST_WRITES; 1920 grbm_gfx_index = INSTANCE_BROADCAST_WRITES;
1692 1921
@@ -1769,9 +1998,16 @@ static void evergreen_gpu_init(struct radeon_device *rdev)
1769 GS_PRIO(2) | 1998 GS_PRIO(2) |
1770 ES_PRIO(3)); 1999 ES_PRIO(3));
1771 2000
1772 if (rdev->family == CHIP_CEDAR) 2001 switch (rdev->family) {
2002 case CHIP_CEDAR:
2003 case CHIP_PALM:
2004 case CHIP_CAICOS:
1773 /* no vertex cache */ 2005 /* no vertex cache */
1774 sq_config &= ~VC_ENABLE; 2006 sq_config &= ~VC_ENABLE;
2007 break;
2008 default:
2009 break;
2010 }
1775 2011
1776 sq_lds_resource_mgmt = RREG32(SQ_LDS_RESOURCE_MGMT); 2012 sq_lds_resource_mgmt = RREG32(SQ_LDS_RESOURCE_MGMT);
1777 2013
@@ -1783,10 +2019,15 @@ static void evergreen_gpu_init(struct radeon_device *rdev)
1783 sq_gpr_resource_mgmt_3 = NUM_HS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 3 / 32); 2019 sq_gpr_resource_mgmt_3 = NUM_HS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 3 / 32);
1784 sq_gpr_resource_mgmt_3 |= NUM_LS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 3 / 32); 2020 sq_gpr_resource_mgmt_3 |= NUM_LS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 3 / 32);
1785 2021
1786 if (rdev->family == CHIP_CEDAR) 2022 switch (rdev->family) {
2023 case CHIP_CEDAR:
2024 case CHIP_PALM:
1787 ps_thread_count = 96; 2025 ps_thread_count = 96;
1788 else 2026 break;
2027 default:
1789 ps_thread_count = 128; 2028 ps_thread_count = 128;
2029 break;
2030 }
1790 2031
1791 sq_thread_resource_mgmt = NUM_PS_THREADS(ps_thread_count); 2032 sq_thread_resource_mgmt = NUM_PS_THREADS(ps_thread_count);
1792 sq_thread_resource_mgmt |= NUM_VS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8); 2033 sq_thread_resource_mgmt |= NUM_VS_THREADS((((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8);
@@ -1817,10 +2058,16 @@ static void evergreen_gpu_init(struct radeon_device *rdev)
1817 WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) | 2058 WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
1818 FORCE_EOV_MAX_REZ_CNT(255))); 2059 FORCE_EOV_MAX_REZ_CNT(255)));
1819 2060
1820 if (rdev->family == CHIP_CEDAR) 2061 switch (rdev->family) {
2062 case CHIP_CEDAR:
2063 case CHIP_PALM:
2064 case CHIP_CAICOS:
1821 vgt_cache_invalidation = CACHE_INVALIDATION(TC_ONLY); 2065 vgt_cache_invalidation = CACHE_INVALIDATION(TC_ONLY);
1822 else 2066 break;
2067 default:
1823 vgt_cache_invalidation = CACHE_INVALIDATION(VC_AND_TC); 2068 vgt_cache_invalidation = CACHE_INVALIDATION(VC_AND_TC);
2069 break;
2070 }
1824 vgt_cache_invalidation |= AUTO_INVLD_EN(ES_AND_GS_AUTO); 2071 vgt_cache_invalidation |= AUTO_INVLD_EN(ES_AND_GS_AUTO);
1825 WREG32(VGT_CACHE_INVALIDATION, vgt_cache_invalidation); 2072 WREG32(VGT_CACHE_INVALIDATION, vgt_cache_invalidation);
1826 2073
@@ -1904,12 +2151,18 @@ int evergreen_mc_init(struct radeon_device *rdev)
1904 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0); 2151 rdev->mc.aper_base = pci_resource_start(rdev->pdev, 0);
1905 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0); 2152 rdev->mc.aper_size = pci_resource_len(rdev->pdev, 0);
1906 /* Setup GPU memory space */ 2153 /* Setup GPU memory space */
1907 /* size in MB on evergreen */ 2154 if (rdev->flags & RADEON_IS_IGP) {
1908 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024; 2155 /* size in bytes on fusion */
1909 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024; 2156 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
2157 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
2158 } else {
2159 /* size in MB on evergreen */
2160 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
2161 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
2162 }
1910 rdev->mc.visible_vram_size = rdev->mc.aper_size; 2163 rdev->mc.visible_vram_size = rdev->mc.aper_size;
1911 rdev->mc.active_vram_size = rdev->mc.visible_vram_size; 2164 rdev->mc.active_vram_size = rdev->mc.visible_vram_size;
1912 r600_vram_gtt_location(rdev, &rdev->mc); 2165 r700_vram_gtt_location(rdev, &rdev->mc);
1913 radeon_update_bandwidth_info(rdev); 2166 radeon_update_bandwidth_info(rdev);
1914 2167
1915 return 0; 2168 return 0;
@@ -1917,8 +2170,30 @@ int evergreen_mc_init(struct radeon_device *rdev)
1917 2170
1918bool evergreen_gpu_is_lockup(struct radeon_device *rdev) 2171bool evergreen_gpu_is_lockup(struct radeon_device *rdev)
1919{ 2172{
1920 /* FIXME: implement for evergreen */ 2173 u32 srbm_status;
1921 return false; 2174 u32 grbm_status;
2175 u32 grbm_status_se0, grbm_status_se1;
2176 struct r100_gpu_lockup *lockup = &rdev->config.evergreen.lockup;
2177 int r;
2178
2179 srbm_status = RREG32(SRBM_STATUS);
2180 grbm_status = RREG32(GRBM_STATUS);
2181 grbm_status_se0 = RREG32(GRBM_STATUS_SE0);
2182 grbm_status_se1 = RREG32(GRBM_STATUS_SE1);
2183 if (!(grbm_status & GUI_ACTIVE)) {
2184 r100_gpu_lockup_update(lockup, &rdev->cp);
2185 return false;
2186 }
2187 /* force CP activities */
2188 r = radeon_ring_lock(rdev, 2);
2189 if (!r) {
2190 /* PACKET2 NOP */
2191 radeon_ring_write(rdev, 0x80000000);
2192 radeon_ring_write(rdev, 0x80000000);
2193 radeon_ring_unlock_commit(rdev);
2194 }
2195 rdev->cp.rptr = RREG32(CP_RB_RPTR);
2196 return r100_gpu_cp_is_lockup(rdev, lockup, &rdev->cp);
1922} 2197}
1923 2198
1924static int evergreen_gpu_soft_reset(struct radeon_device *rdev) 2199static int evergreen_gpu_soft_reset(struct radeon_device *rdev)
@@ -2011,17 +2286,21 @@ void evergreen_disable_interrupt_state(struct radeon_device *rdev)
2011 WREG32(GRBM_INT_CNTL, 0); 2286 WREG32(GRBM_INT_CNTL, 0);
2012 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); 2287 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
2013 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); 2288 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
2014 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0); 2289 if (!(rdev->flags & RADEON_IS_IGP)) {
2015 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0); 2290 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
2016 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0); 2291 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
2017 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0); 2292 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
2293 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
2294 }
2018 2295
2019 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0); 2296 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
2020 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0); 2297 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
2021 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0); 2298 if (!(rdev->flags & RADEON_IS_IGP)) {
2022 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0); 2299 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
2023 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0); 2300 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
2024 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0); 2301 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
2302 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
2303 }
2025 2304
2026 WREG32(DACA_AUTODETECT_INT_CONTROL, 0); 2305 WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
2027 WREG32(DACB_AUTODETECT_INT_CONTROL, 0); 2306 WREG32(DACB_AUTODETECT_INT_CONTROL, 0);
@@ -2047,6 +2326,7 @@ int evergreen_irq_set(struct radeon_device *rdev)
2047 u32 crtc1 = 0, crtc2 = 0, crtc3 = 0, crtc4 = 0, crtc5 = 0, crtc6 = 0; 2326 u32 crtc1 = 0, crtc2 = 0, crtc3 = 0, crtc4 = 0, crtc5 = 0, crtc6 = 0;
2048 u32 hpd1, hpd2, hpd3, hpd4, hpd5, hpd6; 2327 u32 hpd1, hpd2, hpd3, hpd4, hpd5, hpd6;
2049 u32 grbm_int_cntl = 0; 2328 u32 grbm_int_cntl = 0;
2329 u32 grph1 = 0, grph2 = 0, grph3 = 0, grph4 = 0, grph5 = 0, grph6 = 0;
2050 2330
2051 if (!rdev->irq.installed) { 2331 if (!rdev->irq.installed) {
2052 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n"); 2332 WARN(1, "Can't enable IRQ/MSI because no handler is installed\n");
@@ -2072,27 +2352,33 @@ int evergreen_irq_set(struct radeon_device *rdev)
2072 cp_int_cntl |= RB_INT_ENABLE; 2352 cp_int_cntl |= RB_INT_ENABLE;
2073 cp_int_cntl |= TIME_STAMP_INT_ENABLE; 2353 cp_int_cntl |= TIME_STAMP_INT_ENABLE;
2074 } 2354 }
2075 if (rdev->irq.crtc_vblank_int[0]) { 2355 if (rdev->irq.crtc_vblank_int[0] ||
2356 rdev->irq.pflip[0]) {
2076 DRM_DEBUG("evergreen_irq_set: vblank 0\n"); 2357 DRM_DEBUG("evergreen_irq_set: vblank 0\n");
2077 crtc1 |= VBLANK_INT_MASK; 2358 crtc1 |= VBLANK_INT_MASK;
2078 } 2359 }
2079 if (rdev->irq.crtc_vblank_int[1]) { 2360 if (rdev->irq.crtc_vblank_int[1] ||
2361 rdev->irq.pflip[1]) {
2080 DRM_DEBUG("evergreen_irq_set: vblank 1\n"); 2362 DRM_DEBUG("evergreen_irq_set: vblank 1\n");
2081 crtc2 |= VBLANK_INT_MASK; 2363 crtc2 |= VBLANK_INT_MASK;
2082 } 2364 }
2083 if (rdev->irq.crtc_vblank_int[2]) { 2365 if (rdev->irq.crtc_vblank_int[2] ||
2366 rdev->irq.pflip[2]) {
2084 DRM_DEBUG("evergreen_irq_set: vblank 2\n"); 2367 DRM_DEBUG("evergreen_irq_set: vblank 2\n");
2085 crtc3 |= VBLANK_INT_MASK; 2368 crtc3 |= VBLANK_INT_MASK;
2086 } 2369 }
2087 if (rdev->irq.crtc_vblank_int[3]) { 2370 if (rdev->irq.crtc_vblank_int[3] ||
2371 rdev->irq.pflip[3]) {
2088 DRM_DEBUG("evergreen_irq_set: vblank 3\n"); 2372 DRM_DEBUG("evergreen_irq_set: vblank 3\n");
2089 crtc4 |= VBLANK_INT_MASK; 2373 crtc4 |= VBLANK_INT_MASK;
2090 } 2374 }
2091 if (rdev->irq.crtc_vblank_int[4]) { 2375 if (rdev->irq.crtc_vblank_int[4] ||
2376 rdev->irq.pflip[4]) {
2092 DRM_DEBUG("evergreen_irq_set: vblank 4\n"); 2377 DRM_DEBUG("evergreen_irq_set: vblank 4\n");
2093 crtc5 |= VBLANK_INT_MASK; 2378 crtc5 |= VBLANK_INT_MASK;
2094 } 2379 }
2095 if (rdev->irq.crtc_vblank_int[5]) { 2380 if (rdev->irq.crtc_vblank_int[5] ||
2381 rdev->irq.pflip[5]) {
2096 DRM_DEBUG("evergreen_irq_set: vblank 5\n"); 2382 DRM_DEBUG("evergreen_irq_set: vblank 5\n");
2097 crtc6 |= VBLANK_INT_MASK; 2383 crtc6 |= VBLANK_INT_MASK;
2098 } 2384 }
@@ -2130,10 +2416,19 @@ int evergreen_irq_set(struct radeon_device *rdev)
2130 2416
2131 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1); 2417 WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1);
2132 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, crtc2); 2418 WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, crtc2);
2133 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, crtc3); 2419 if (!(rdev->flags & RADEON_IS_IGP)) {
2134 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, crtc4); 2420 WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, crtc3);
2135 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, crtc5); 2421 WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, crtc4);
2136 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6); 2422 WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, crtc5);
2423 WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6);
2424 }
2425
2426 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, grph1);
2427 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, grph2);
2428 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, grph3);
2429 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, grph4);
2430 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, grph5);
2431 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, grph6);
2137 2432
2138 WREG32(DC_HPD1_INT_CONTROL, hpd1); 2433 WREG32(DC_HPD1_INT_CONTROL, hpd1);
2139 WREG32(DC_HPD2_INT_CONTROL, hpd2); 2434 WREG32(DC_HPD2_INT_CONTROL, hpd2);
@@ -2145,79 +2440,92 @@ int evergreen_irq_set(struct radeon_device *rdev)
2145 return 0; 2440 return 0;
2146} 2441}
2147 2442
2148static inline void evergreen_irq_ack(struct radeon_device *rdev, 2443static inline void evergreen_irq_ack(struct radeon_device *rdev)
2149 u32 *disp_int,
2150 u32 *disp_int_cont,
2151 u32 *disp_int_cont2,
2152 u32 *disp_int_cont3,
2153 u32 *disp_int_cont4,
2154 u32 *disp_int_cont5)
2155{ 2444{
2156 u32 tmp; 2445 u32 tmp;
2157 2446
2158 *disp_int = RREG32(DISP_INTERRUPT_STATUS); 2447 rdev->irq.stat_regs.evergreen.disp_int = RREG32(DISP_INTERRUPT_STATUS);
2159 *disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE); 2448 rdev->irq.stat_regs.evergreen.disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
2160 *disp_int_cont2 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE2); 2449 rdev->irq.stat_regs.evergreen.disp_int_cont2 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE2);
2161 *disp_int_cont3 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE3); 2450 rdev->irq.stat_regs.evergreen.disp_int_cont3 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE3);
2162 *disp_int_cont4 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE4); 2451 rdev->irq.stat_regs.evergreen.disp_int_cont4 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE4);
2163 *disp_int_cont5 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE5); 2452 rdev->irq.stat_regs.evergreen.disp_int_cont5 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE5);
2164 2453 rdev->irq.stat_regs.evergreen.d1grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET);
2165 if (*disp_int & LB_D1_VBLANK_INTERRUPT) 2454 rdev->irq.stat_regs.evergreen.d2grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET);
2455 rdev->irq.stat_regs.evergreen.d3grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET);
2456 rdev->irq.stat_regs.evergreen.d4grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET);
2457 rdev->irq.stat_regs.evergreen.d5grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET);
2458 rdev->irq.stat_regs.evergreen.d6grph_int = RREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET);
2459
2460 if (rdev->irq.stat_regs.evergreen.d1grph_int & GRPH_PFLIP_INT_OCCURRED)
2461 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2462 if (rdev->irq.stat_regs.evergreen.d2grph_int & GRPH_PFLIP_INT_OCCURRED)
2463 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2464 if (rdev->irq.stat_regs.evergreen.d3grph_int & GRPH_PFLIP_INT_OCCURRED)
2465 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2466 if (rdev->irq.stat_regs.evergreen.d4grph_int & GRPH_PFLIP_INT_OCCURRED)
2467 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2468 if (rdev->irq.stat_regs.evergreen.d5grph_int & GRPH_PFLIP_INT_OCCURRED)
2469 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2470 if (rdev->irq.stat_regs.evergreen.d6grph_int & GRPH_PFLIP_INT_OCCURRED)
2471 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, GRPH_PFLIP_INT_CLEAR);
2472
2473 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT)
2166 WREG32(VBLANK_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VBLANK_ACK); 2474 WREG32(VBLANK_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VBLANK_ACK);
2167 if (*disp_int & LB_D1_VLINE_INTERRUPT) 2475 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT)
2168 WREG32(VLINE_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VLINE_ACK); 2476 WREG32(VLINE_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VLINE_ACK);
2169 2477
2170 if (*disp_int_cont & LB_D2_VBLANK_INTERRUPT) 2478 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT)
2171 WREG32(VBLANK_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VBLANK_ACK); 2479 WREG32(VBLANK_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VBLANK_ACK);
2172 if (*disp_int_cont & LB_D2_VLINE_INTERRUPT) 2480 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT)
2173 WREG32(VLINE_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VLINE_ACK); 2481 WREG32(VLINE_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VLINE_ACK);
2174 2482
2175 if (*disp_int_cont2 & LB_D3_VBLANK_INTERRUPT) 2483 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT)
2176 WREG32(VBLANK_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VBLANK_ACK); 2484 WREG32(VBLANK_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VBLANK_ACK);
2177 if (*disp_int_cont2 & LB_D3_VLINE_INTERRUPT) 2485 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT)
2178 WREG32(VLINE_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VLINE_ACK); 2486 WREG32(VLINE_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VLINE_ACK);
2179 2487
2180 if (*disp_int_cont3 & LB_D4_VBLANK_INTERRUPT) 2488 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT)
2181 WREG32(VBLANK_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VBLANK_ACK); 2489 WREG32(VBLANK_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VBLANK_ACK);
2182 if (*disp_int_cont3 & LB_D4_VLINE_INTERRUPT) 2490 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT)
2183 WREG32(VLINE_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VLINE_ACK); 2491 WREG32(VLINE_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VLINE_ACK);
2184 2492
2185 if (*disp_int_cont4 & LB_D5_VBLANK_INTERRUPT) 2493 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT)
2186 WREG32(VBLANK_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VBLANK_ACK); 2494 WREG32(VBLANK_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VBLANK_ACK);
2187 if (*disp_int_cont4 & LB_D5_VLINE_INTERRUPT) 2495 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT)
2188 WREG32(VLINE_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VLINE_ACK); 2496 WREG32(VLINE_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VLINE_ACK);
2189 2497
2190 if (*disp_int_cont5 & LB_D6_VBLANK_INTERRUPT) 2498 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT)
2191 WREG32(VBLANK_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VBLANK_ACK); 2499 WREG32(VBLANK_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VBLANK_ACK);
2192 if (*disp_int_cont5 & LB_D6_VLINE_INTERRUPT) 2500 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT)
2193 WREG32(VLINE_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VLINE_ACK); 2501 WREG32(VLINE_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VLINE_ACK);
2194 2502
2195 if (*disp_int & DC_HPD1_INTERRUPT) { 2503 if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) {
2196 tmp = RREG32(DC_HPD1_INT_CONTROL); 2504 tmp = RREG32(DC_HPD1_INT_CONTROL);
2197 tmp |= DC_HPDx_INT_ACK; 2505 tmp |= DC_HPDx_INT_ACK;
2198 WREG32(DC_HPD1_INT_CONTROL, tmp); 2506 WREG32(DC_HPD1_INT_CONTROL, tmp);
2199 } 2507 }
2200 if (*disp_int_cont & DC_HPD2_INTERRUPT) { 2508 if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT) {
2201 tmp = RREG32(DC_HPD2_INT_CONTROL); 2509 tmp = RREG32(DC_HPD2_INT_CONTROL);
2202 tmp |= DC_HPDx_INT_ACK; 2510 tmp |= DC_HPDx_INT_ACK;
2203 WREG32(DC_HPD2_INT_CONTROL, tmp); 2511 WREG32(DC_HPD2_INT_CONTROL, tmp);
2204 } 2512 }
2205 if (*disp_int_cont2 & DC_HPD3_INTERRUPT) { 2513 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT) {
2206 tmp = RREG32(DC_HPD3_INT_CONTROL); 2514 tmp = RREG32(DC_HPD3_INT_CONTROL);
2207 tmp |= DC_HPDx_INT_ACK; 2515 tmp |= DC_HPDx_INT_ACK;
2208 WREG32(DC_HPD3_INT_CONTROL, tmp); 2516 WREG32(DC_HPD3_INT_CONTROL, tmp);
2209 } 2517 }
2210 if (*disp_int_cont3 & DC_HPD4_INTERRUPT) { 2518 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT) {
2211 tmp = RREG32(DC_HPD4_INT_CONTROL); 2519 tmp = RREG32(DC_HPD4_INT_CONTROL);
2212 tmp |= DC_HPDx_INT_ACK; 2520 tmp |= DC_HPDx_INT_ACK;
2213 WREG32(DC_HPD4_INT_CONTROL, tmp); 2521 WREG32(DC_HPD4_INT_CONTROL, tmp);
2214 } 2522 }
2215 if (*disp_int_cont4 & DC_HPD5_INTERRUPT) { 2523 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT) {
2216 tmp = RREG32(DC_HPD5_INT_CONTROL); 2524 tmp = RREG32(DC_HPD5_INT_CONTROL);
2217 tmp |= DC_HPDx_INT_ACK; 2525 tmp |= DC_HPDx_INT_ACK;
2218 WREG32(DC_HPD5_INT_CONTROL, tmp); 2526 WREG32(DC_HPD5_INT_CONTROL, tmp);
2219 } 2527 }
2220 if (*disp_int_cont5 & DC_HPD6_INTERRUPT) { 2528 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) {
2221 tmp = RREG32(DC_HPD5_INT_CONTROL); 2529 tmp = RREG32(DC_HPD5_INT_CONTROL);
2222 tmp |= DC_HPDx_INT_ACK; 2530 tmp |= DC_HPDx_INT_ACK;
2223 WREG32(DC_HPD6_INT_CONTROL, tmp); 2531 WREG32(DC_HPD6_INT_CONTROL, tmp);
@@ -2226,14 +2534,10 @@ static inline void evergreen_irq_ack(struct radeon_device *rdev,
2226 2534
2227void evergreen_irq_disable(struct radeon_device *rdev) 2535void evergreen_irq_disable(struct radeon_device *rdev)
2228{ 2536{
2229 u32 disp_int, disp_int_cont, disp_int_cont2;
2230 u32 disp_int_cont3, disp_int_cont4, disp_int_cont5;
2231
2232 r600_disable_interrupts(rdev); 2537 r600_disable_interrupts(rdev);
2233 /* Wait and acknowledge irq */ 2538 /* Wait and acknowledge irq */
2234 mdelay(1); 2539 mdelay(1);
2235 evergreen_irq_ack(rdev, &disp_int, &disp_int_cont, &disp_int_cont2, 2540 evergreen_irq_ack(rdev);
2236 &disp_int_cont3, &disp_int_cont4, &disp_int_cont5);
2237 evergreen_disable_interrupt_state(rdev); 2541 evergreen_disable_interrupt_state(rdev);
2238} 2542}
2239 2543
@@ -2273,8 +2577,6 @@ int evergreen_irq_process(struct radeon_device *rdev)
2273 u32 rptr = rdev->ih.rptr; 2577 u32 rptr = rdev->ih.rptr;
2274 u32 src_id, src_data; 2578 u32 src_id, src_data;
2275 u32 ring_index; 2579 u32 ring_index;
2276 u32 disp_int, disp_int_cont, disp_int_cont2;
2277 u32 disp_int_cont3, disp_int_cont4, disp_int_cont5;
2278 unsigned long flags; 2580 unsigned long flags;
2279 bool queue_hotplug = false; 2581 bool queue_hotplug = false;
2280 2582
@@ -2295,8 +2597,7 @@ int evergreen_irq_process(struct radeon_device *rdev)
2295 2597
2296restart_ih: 2598restart_ih:
2297 /* display interrupts */ 2599 /* display interrupts */
2298 evergreen_irq_ack(rdev, &disp_int, &disp_int_cont, &disp_int_cont2, 2600 evergreen_irq_ack(rdev);
2299 &disp_int_cont3, &disp_int_cont4, &disp_int_cont5);
2300 2601
2301 rdev->ih.wptr = wptr; 2602 rdev->ih.wptr = wptr;
2302 while (rptr != wptr) { 2603 while (rptr != wptr) {
@@ -2309,17 +2610,21 @@ restart_ih:
2309 case 1: /* D1 vblank/vline */ 2610 case 1: /* D1 vblank/vline */
2310 switch (src_data) { 2611 switch (src_data) {
2311 case 0: /* D1 vblank */ 2612 case 0: /* D1 vblank */
2312 if (disp_int & LB_D1_VBLANK_INTERRUPT) { 2613 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VBLANK_INTERRUPT) {
2313 drm_handle_vblank(rdev->ddev, 0); 2614 if (rdev->irq.crtc_vblank_int[0]) {
2314 rdev->pm.vblank_sync = true; 2615 drm_handle_vblank(rdev->ddev, 0);
2315 wake_up(&rdev->irq.vblank_queue); 2616 rdev->pm.vblank_sync = true;
2316 disp_int &= ~LB_D1_VBLANK_INTERRUPT; 2617 wake_up(&rdev->irq.vblank_queue);
2618 }
2619 if (rdev->irq.pflip[0])
2620 radeon_crtc_handle_flip(rdev, 0);
2621 rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VBLANK_INTERRUPT;
2317 DRM_DEBUG("IH: D1 vblank\n"); 2622 DRM_DEBUG("IH: D1 vblank\n");
2318 } 2623 }
2319 break; 2624 break;
2320 case 1: /* D1 vline */ 2625 case 1: /* D1 vline */
2321 if (disp_int & LB_D1_VLINE_INTERRUPT) { 2626 if (rdev->irq.stat_regs.evergreen.disp_int & LB_D1_VLINE_INTERRUPT) {
2322 disp_int &= ~LB_D1_VLINE_INTERRUPT; 2627 rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VLINE_INTERRUPT;
2323 DRM_DEBUG("IH: D1 vline\n"); 2628 DRM_DEBUG("IH: D1 vline\n");
2324 } 2629 }
2325 break; 2630 break;
@@ -2331,17 +2636,21 @@ restart_ih:
2331 case 2: /* D2 vblank/vline */ 2636 case 2: /* D2 vblank/vline */
2332 switch (src_data) { 2637 switch (src_data) {
2333 case 0: /* D2 vblank */ 2638 case 0: /* D2 vblank */
2334 if (disp_int_cont & LB_D2_VBLANK_INTERRUPT) { 2639 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VBLANK_INTERRUPT) {
2335 drm_handle_vblank(rdev->ddev, 1); 2640 if (rdev->irq.crtc_vblank_int[1]) {
2336 rdev->pm.vblank_sync = true; 2641 drm_handle_vblank(rdev->ddev, 1);
2337 wake_up(&rdev->irq.vblank_queue); 2642 rdev->pm.vblank_sync = true;
2338 disp_int_cont &= ~LB_D2_VBLANK_INTERRUPT; 2643 wake_up(&rdev->irq.vblank_queue);
2644 }
2645 if (rdev->irq.pflip[1])
2646 radeon_crtc_handle_flip(rdev, 1);
2647 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VBLANK_INTERRUPT;
2339 DRM_DEBUG("IH: D2 vblank\n"); 2648 DRM_DEBUG("IH: D2 vblank\n");
2340 } 2649 }
2341 break; 2650 break;
2342 case 1: /* D2 vline */ 2651 case 1: /* D2 vline */
2343 if (disp_int_cont & LB_D2_VLINE_INTERRUPT) { 2652 if (rdev->irq.stat_regs.evergreen.disp_int_cont & LB_D2_VLINE_INTERRUPT) {
2344 disp_int_cont &= ~LB_D2_VLINE_INTERRUPT; 2653 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VLINE_INTERRUPT;
2345 DRM_DEBUG("IH: D2 vline\n"); 2654 DRM_DEBUG("IH: D2 vline\n");
2346 } 2655 }
2347 break; 2656 break;
@@ -2353,17 +2662,21 @@ restart_ih:
2353 case 3: /* D3 vblank/vline */ 2662 case 3: /* D3 vblank/vline */
2354 switch (src_data) { 2663 switch (src_data) {
2355 case 0: /* D3 vblank */ 2664 case 0: /* D3 vblank */
2356 if (disp_int_cont2 & LB_D3_VBLANK_INTERRUPT) { 2665 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VBLANK_INTERRUPT) {
2357 drm_handle_vblank(rdev->ddev, 2); 2666 if (rdev->irq.crtc_vblank_int[2]) {
2358 rdev->pm.vblank_sync = true; 2667 drm_handle_vblank(rdev->ddev, 2);
2359 wake_up(&rdev->irq.vblank_queue); 2668 rdev->pm.vblank_sync = true;
2360 disp_int_cont2 &= ~LB_D3_VBLANK_INTERRUPT; 2669 wake_up(&rdev->irq.vblank_queue);
2670 }
2671 if (rdev->irq.pflip[2])
2672 radeon_crtc_handle_flip(rdev, 2);
2673 rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VBLANK_INTERRUPT;
2361 DRM_DEBUG("IH: D3 vblank\n"); 2674 DRM_DEBUG("IH: D3 vblank\n");
2362 } 2675 }
2363 break; 2676 break;
2364 case 1: /* D3 vline */ 2677 case 1: /* D3 vline */
2365 if (disp_int_cont2 & LB_D3_VLINE_INTERRUPT) { 2678 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & LB_D3_VLINE_INTERRUPT) {
2366 disp_int_cont2 &= ~LB_D3_VLINE_INTERRUPT; 2679 rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VLINE_INTERRUPT;
2367 DRM_DEBUG("IH: D3 vline\n"); 2680 DRM_DEBUG("IH: D3 vline\n");
2368 } 2681 }
2369 break; 2682 break;
@@ -2375,17 +2688,21 @@ restart_ih:
2375 case 4: /* D4 vblank/vline */ 2688 case 4: /* D4 vblank/vline */
2376 switch (src_data) { 2689 switch (src_data) {
2377 case 0: /* D4 vblank */ 2690 case 0: /* D4 vblank */
2378 if (disp_int_cont3 & LB_D4_VBLANK_INTERRUPT) { 2691 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VBLANK_INTERRUPT) {
2379 drm_handle_vblank(rdev->ddev, 3); 2692 if (rdev->irq.crtc_vblank_int[3]) {
2380 rdev->pm.vblank_sync = true; 2693 drm_handle_vblank(rdev->ddev, 3);
2381 wake_up(&rdev->irq.vblank_queue); 2694 rdev->pm.vblank_sync = true;
2382 disp_int_cont3 &= ~LB_D4_VBLANK_INTERRUPT; 2695 wake_up(&rdev->irq.vblank_queue);
2696 }
2697 if (rdev->irq.pflip[3])
2698 radeon_crtc_handle_flip(rdev, 3);
2699 rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VBLANK_INTERRUPT;
2383 DRM_DEBUG("IH: D4 vblank\n"); 2700 DRM_DEBUG("IH: D4 vblank\n");
2384 } 2701 }
2385 break; 2702 break;
2386 case 1: /* D4 vline */ 2703 case 1: /* D4 vline */
2387 if (disp_int_cont3 & LB_D4_VLINE_INTERRUPT) { 2704 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & LB_D4_VLINE_INTERRUPT) {
2388 disp_int_cont3 &= ~LB_D4_VLINE_INTERRUPT; 2705 rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VLINE_INTERRUPT;
2389 DRM_DEBUG("IH: D4 vline\n"); 2706 DRM_DEBUG("IH: D4 vline\n");
2390 } 2707 }
2391 break; 2708 break;
@@ -2397,17 +2714,21 @@ restart_ih:
2397 case 5: /* D5 vblank/vline */ 2714 case 5: /* D5 vblank/vline */
2398 switch (src_data) { 2715 switch (src_data) {
2399 case 0: /* D5 vblank */ 2716 case 0: /* D5 vblank */
2400 if (disp_int_cont4 & LB_D5_VBLANK_INTERRUPT) { 2717 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VBLANK_INTERRUPT) {
2401 drm_handle_vblank(rdev->ddev, 4); 2718 if (rdev->irq.crtc_vblank_int[4]) {
2402 rdev->pm.vblank_sync = true; 2719 drm_handle_vblank(rdev->ddev, 4);
2403 wake_up(&rdev->irq.vblank_queue); 2720 rdev->pm.vblank_sync = true;
2404 disp_int_cont4 &= ~LB_D5_VBLANK_INTERRUPT; 2721 wake_up(&rdev->irq.vblank_queue);
2722 }
2723 if (rdev->irq.pflip[4])
2724 radeon_crtc_handle_flip(rdev, 4);
2725 rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VBLANK_INTERRUPT;
2405 DRM_DEBUG("IH: D5 vblank\n"); 2726 DRM_DEBUG("IH: D5 vblank\n");
2406 } 2727 }
2407 break; 2728 break;
2408 case 1: /* D5 vline */ 2729 case 1: /* D5 vline */
2409 if (disp_int_cont4 & LB_D5_VLINE_INTERRUPT) { 2730 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & LB_D5_VLINE_INTERRUPT) {
2410 disp_int_cont4 &= ~LB_D5_VLINE_INTERRUPT; 2731 rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VLINE_INTERRUPT;
2411 DRM_DEBUG("IH: D5 vline\n"); 2732 DRM_DEBUG("IH: D5 vline\n");
2412 } 2733 }
2413 break; 2734 break;
@@ -2419,17 +2740,21 @@ restart_ih:
2419 case 6: /* D6 vblank/vline */ 2740 case 6: /* D6 vblank/vline */
2420 switch (src_data) { 2741 switch (src_data) {
2421 case 0: /* D6 vblank */ 2742 case 0: /* D6 vblank */
2422 if (disp_int_cont5 & LB_D6_VBLANK_INTERRUPT) { 2743 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VBLANK_INTERRUPT) {
2423 drm_handle_vblank(rdev->ddev, 5); 2744 if (rdev->irq.crtc_vblank_int[5]) {
2424 rdev->pm.vblank_sync = true; 2745 drm_handle_vblank(rdev->ddev, 5);
2425 wake_up(&rdev->irq.vblank_queue); 2746 rdev->pm.vblank_sync = true;
2426 disp_int_cont5 &= ~LB_D6_VBLANK_INTERRUPT; 2747 wake_up(&rdev->irq.vblank_queue);
2748 }
2749 if (rdev->irq.pflip[5])
2750 radeon_crtc_handle_flip(rdev, 5);
2751 rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VBLANK_INTERRUPT;
2427 DRM_DEBUG("IH: D6 vblank\n"); 2752 DRM_DEBUG("IH: D6 vblank\n");
2428 } 2753 }
2429 break; 2754 break;
2430 case 1: /* D6 vline */ 2755 case 1: /* D6 vline */
2431 if (disp_int_cont5 & LB_D6_VLINE_INTERRUPT) { 2756 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & LB_D6_VLINE_INTERRUPT) {
2432 disp_int_cont5 &= ~LB_D6_VLINE_INTERRUPT; 2757 rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VLINE_INTERRUPT;
2433 DRM_DEBUG("IH: D6 vline\n"); 2758 DRM_DEBUG("IH: D6 vline\n");
2434 } 2759 }
2435 break; 2760 break;
@@ -2441,43 +2766,43 @@ restart_ih:
2441 case 42: /* HPD hotplug */ 2766 case 42: /* HPD hotplug */
2442 switch (src_data) { 2767 switch (src_data) {
2443 case 0: 2768 case 0:
2444 if (disp_int & DC_HPD1_INTERRUPT) { 2769 if (rdev->irq.stat_regs.evergreen.disp_int & DC_HPD1_INTERRUPT) {
2445 disp_int &= ~DC_HPD1_INTERRUPT; 2770 rdev->irq.stat_regs.evergreen.disp_int &= ~DC_HPD1_INTERRUPT;
2446 queue_hotplug = true; 2771 queue_hotplug = true;
2447 DRM_DEBUG("IH: HPD1\n"); 2772 DRM_DEBUG("IH: HPD1\n");
2448 } 2773 }
2449 break; 2774 break;
2450 case 1: 2775 case 1:
2451 if (disp_int_cont & DC_HPD2_INTERRUPT) { 2776 if (rdev->irq.stat_regs.evergreen.disp_int_cont & DC_HPD2_INTERRUPT) {
2452 disp_int_cont &= ~DC_HPD2_INTERRUPT; 2777 rdev->irq.stat_regs.evergreen.disp_int_cont &= ~DC_HPD2_INTERRUPT;
2453 queue_hotplug = true; 2778 queue_hotplug = true;
2454 DRM_DEBUG("IH: HPD2\n"); 2779 DRM_DEBUG("IH: HPD2\n");
2455 } 2780 }
2456 break; 2781 break;
2457 case 2: 2782 case 2:
2458 if (disp_int_cont2 & DC_HPD3_INTERRUPT) { 2783 if (rdev->irq.stat_regs.evergreen.disp_int_cont2 & DC_HPD3_INTERRUPT) {
2459 disp_int_cont2 &= ~DC_HPD3_INTERRUPT; 2784 rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~DC_HPD3_INTERRUPT;
2460 queue_hotplug = true; 2785 queue_hotplug = true;
2461 DRM_DEBUG("IH: HPD3\n"); 2786 DRM_DEBUG("IH: HPD3\n");
2462 } 2787 }
2463 break; 2788 break;
2464 case 3: 2789 case 3:
2465 if (disp_int_cont3 & DC_HPD4_INTERRUPT) { 2790 if (rdev->irq.stat_regs.evergreen.disp_int_cont3 & DC_HPD4_INTERRUPT) {
2466 disp_int_cont3 &= ~DC_HPD4_INTERRUPT; 2791 rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~DC_HPD4_INTERRUPT;
2467 queue_hotplug = true; 2792 queue_hotplug = true;
2468 DRM_DEBUG("IH: HPD4\n"); 2793 DRM_DEBUG("IH: HPD4\n");
2469 } 2794 }
2470 break; 2795 break;
2471 case 4: 2796 case 4:
2472 if (disp_int_cont4 & DC_HPD5_INTERRUPT) { 2797 if (rdev->irq.stat_regs.evergreen.disp_int_cont4 & DC_HPD5_INTERRUPT) {
2473 disp_int_cont4 &= ~DC_HPD5_INTERRUPT; 2798 rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~DC_HPD5_INTERRUPT;
2474 queue_hotplug = true; 2799 queue_hotplug = true;
2475 DRM_DEBUG("IH: HPD5\n"); 2800 DRM_DEBUG("IH: HPD5\n");
2476 } 2801 }
2477 break; 2802 break;
2478 case 5: 2803 case 5:
2479 if (disp_int_cont5 & DC_HPD6_INTERRUPT) { 2804 if (rdev->irq.stat_regs.evergreen.disp_int_cont5 & DC_HPD6_INTERRUPT) {
2480 disp_int_cont5 &= ~DC_HPD6_INTERRUPT; 2805 rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~DC_HPD6_INTERRUPT;
2481 queue_hotplug = true; 2806 queue_hotplug = true;
2482 DRM_DEBUG("IH: HPD6\n"); 2807 DRM_DEBUG("IH: HPD6\n");
2483 } 2808 }
@@ -2516,7 +2841,7 @@ restart_ih:
2516 if (wptr != rdev->ih.wptr) 2841 if (wptr != rdev->ih.wptr)
2517 goto restart_ih; 2842 goto restart_ih;
2518 if (queue_hotplug) 2843 if (queue_hotplug)
2519 queue_work(rdev->wq, &rdev->hotplug_work); 2844 schedule_work(&rdev->hotplug_work);
2520 rdev->ih.rptr = rptr; 2845 rdev->ih.rptr = rptr;
2521 WREG32(IH_RB_RPTR, rdev->ih.rptr); 2846 WREG32(IH_RB_RPTR, rdev->ih.rptr);
2522 spin_unlock_irqrestore(&rdev->ih.lock, flags); 2847 spin_unlock_irqrestore(&rdev->ih.lock, flags);
@@ -2527,12 +2852,31 @@ static int evergreen_startup(struct radeon_device *rdev)
2527{ 2852{
2528 int r; 2853 int r;
2529 2854
2530 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) { 2855 /* enable pcie gen2 link */
2531 r = r600_init_microcode(rdev); 2856 if (!ASIC_IS_DCE5(rdev))
2857 evergreen_pcie_gen2_enable(rdev);
2858
2859 if (ASIC_IS_DCE5(rdev)) {
2860 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw || !rdev->mc_fw) {
2861 r = ni_init_microcode(rdev);
2862 if (r) {
2863 DRM_ERROR("Failed to load firmware!\n");
2864 return r;
2865 }
2866 }
2867 r = btc_mc_load_microcode(rdev);
2532 if (r) { 2868 if (r) {
2533 DRM_ERROR("Failed to load firmware!\n"); 2869 DRM_ERROR("Failed to load MC firmware!\n");
2534 return r; 2870 return r;
2535 } 2871 }
2872 } else {
2873 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
2874 r = r600_init_microcode(rdev);
2875 if (r) {
2876 DRM_ERROR("Failed to load firmware!\n");
2877 return r;
2878 }
2879 }
2536 } 2880 }
2537 2881
2538 evergreen_mc_program(rdev); 2882 evergreen_mc_program(rdev);
@@ -2551,6 +2895,11 @@ static int evergreen_startup(struct radeon_device *rdev)
2551 rdev->asic->copy = NULL; 2895 rdev->asic->copy = NULL;
2552 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r); 2896 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
2553 } 2897 }
2898 /* XXX: ontario has problems blitting to gart at the moment */
2899 if (rdev->family == CHIP_PALM) {
2900 rdev->asic->copy = NULL;
2901 rdev->mc.active_vram_size = rdev->mc.visible_vram_size;
2902 }
2554 2903
2555 /* allocate wb buffer */ 2904 /* allocate wb buffer */
2556 r = radeon_wb_init(rdev); 2905 r = radeon_wb_init(rdev);
@@ -2658,12 +3007,16 @@ static bool evergreen_card_posted(struct radeon_device *rdev)
2658 u32 reg; 3007 u32 reg;
2659 3008
2660 /* first check CRTCs */ 3009 /* first check CRTCs */
2661 reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) | 3010 if (rdev->flags & RADEON_IS_IGP)
2662 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET) | 3011 reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) |
2663 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) | 3012 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET);
2664 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET) | 3013 else
2665 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) | 3014 reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) |
2666 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET); 3015 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET) |
3016 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) |
3017 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET) |
3018 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) |
3019 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
2667 if (reg & EVERGREEN_CRTC_MASTER_EN) 3020 if (reg & EVERGREEN_CRTC_MASTER_EN)
2668 return true; 3021 return true;
2669 3022
@@ -2800,3 +3153,52 @@ void evergreen_fini(struct radeon_device *rdev)
2800 rdev->bios = NULL; 3153 rdev->bios = NULL;
2801 radeon_dummy_page_fini(rdev); 3154 radeon_dummy_page_fini(rdev);
2802} 3155}
3156
3157static void evergreen_pcie_gen2_enable(struct radeon_device *rdev)
3158{
3159 u32 link_width_cntl, speed_cntl;
3160
3161 if (rdev->flags & RADEON_IS_IGP)
3162 return;
3163
3164 if (!(rdev->flags & RADEON_IS_PCIE))
3165 return;
3166
3167 /* x2 cards have a special sequence */
3168 if (ASIC_IS_X2(rdev))
3169 return;
3170
3171 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3172 if ((speed_cntl & LC_OTHER_SIDE_EVER_SENT_GEN2) ||
3173 (speed_cntl & LC_OTHER_SIDE_SUPPORTS_GEN2)) {
3174
3175 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
3176 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
3177 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3178
3179 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3180 speed_cntl &= ~LC_TARGET_LINK_SPEED_OVERRIDE_EN;
3181 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3182
3183 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3184 speed_cntl |= LC_CLR_FAILED_SPD_CHANGE_CNT;
3185 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3186
3187 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3188 speed_cntl &= ~LC_CLR_FAILED_SPD_CHANGE_CNT;
3189 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3190
3191 speed_cntl = RREG32_PCIE_P(PCIE_LC_SPEED_CNTL);
3192 speed_cntl |= LC_GEN2_EN_STRAP;
3193 WREG32_PCIE_P(PCIE_LC_SPEED_CNTL, speed_cntl);
3194
3195 } else {
3196 link_width_cntl = RREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL);
3197 /* XXX: only disable it if gen1 bridge vendor == 0x111d or 0x1106 */
3198 if (1)
3199 link_width_cntl |= LC_UPCONFIGURE_DIS;
3200 else
3201 link_width_cntl &= ~LC_UPCONFIGURE_DIS;
3202 WREG32_PCIE_P(PCIE_LC_LINK_WIDTH_CNTL, link_width_cntl);
3203 }
3204}
generated by cgit v1.2.2 (git 2.25.0) at 2025-10-01 02:24:17 -0400