diff options
Diffstat (limited to 'drivers/gpu/drm/radeon/cikd.h')
| -rw-r--r-- | drivers/gpu/drm/radeon/cikd.h | 594 |
1 files changed, 591 insertions, 3 deletions
diff --git a/drivers/gpu/drm/radeon/cikd.h b/drivers/gpu/drm/radeon/cikd.h index 7e9275eaef80..203d2a09a1f5 100644 --- a/drivers/gpu/drm/radeon/cikd.h +++ b/drivers/gpu/drm/radeon/cikd.h | |||
| @@ -28,21 +28,375 @@ | |||
| 28 | 28 | ||
| 29 | #define CIK_RB_BITMAP_WIDTH_PER_SH 2 | 29 | #define CIK_RB_BITMAP_WIDTH_PER_SH 2 |
| 30 | 30 | ||
| 31 | /* DIDT IND registers */ | ||
| 32 | #define DIDT_SQ_CTRL0 0x0 | ||
| 33 | # define DIDT_CTRL_EN (1 << 0) | ||
| 34 | #define DIDT_DB_CTRL0 0x20 | ||
| 35 | #define DIDT_TD_CTRL0 0x40 | ||
| 36 | #define DIDT_TCP_CTRL0 0x60 | ||
| 37 | |||
| 31 | /* SMC IND registers */ | 38 | /* SMC IND registers */ |
| 39 | #define DPM_TABLE_475 0x3F768 | ||
| 40 | # define SamuBootLevel(x) ((x) << 0) | ||
| 41 | # define SamuBootLevel_MASK 0x000000ff | ||
| 42 | # define SamuBootLevel_SHIFT 0 | ||
| 43 | # define AcpBootLevel(x) ((x) << 8) | ||
| 44 | # define AcpBootLevel_MASK 0x0000ff00 | ||
| 45 | # define AcpBootLevel_SHIFT 8 | ||
| 46 | # define VceBootLevel(x) ((x) << 16) | ||
| 47 | # define VceBootLevel_MASK 0x00ff0000 | ||
| 48 | # define VceBootLevel_SHIFT 16 | ||
| 49 | # define UvdBootLevel(x) ((x) << 24) | ||
| 50 | # define UvdBootLevel_MASK 0xff000000 | ||
| 51 | # define UvdBootLevel_SHIFT 24 | ||
| 52 | |||
| 53 | #define FIRMWARE_FLAGS 0x3F800 | ||
| 54 | # define INTERRUPTS_ENABLED (1 << 0) | ||
| 55 | |||
| 56 | #define NB_DPM_CONFIG_1 0x3F9E8 | ||
| 57 | # define Dpm0PgNbPsLo(x) ((x) << 0) | ||
| 58 | # define Dpm0PgNbPsLo_MASK 0x000000ff | ||
| 59 | # define Dpm0PgNbPsLo_SHIFT 0 | ||
| 60 | # define Dpm0PgNbPsHi(x) ((x) << 8) | ||
| 61 | # define Dpm0PgNbPsHi_MASK 0x0000ff00 | ||
| 62 | # define Dpm0PgNbPsHi_SHIFT 8 | ||
| 63 | # define DpmXNbPsLo(x) ((x) << 16) | ||
| 64 | # define DpmXNbPsLo_MASK 0x00ff0000 | ||
| 65 | # define DpmXNbPsLo_SHIFT 16 | ||
| 66 | # define DpmXNbPsHi(x) ((x) << 24) | ||
| 67 | # define DpmXNbPsHi_MASK 0xff000000 | ||
| 68 | # define DpmXNbPsHi_SHIFT 24 | ||
| 69 | |||
| 70 | #define SMC_SYSCON_RESET_CNTL 0x80000000 | ||
| 71 | # define RST_REG (1 << 0) | ||
| 72 | #define SMC_SYSCON_CLOCK_CNTL_0 0x80000004 | ||
| 73 | # define CK_DISABLE (1 << 0) | ||
| 74 | # define CKEN (1 << 24) | ||
| 75 | |||
| 76 | #define SMC_SYSCON_MISC_CNTL 0x80000010 | ||
| 77 | |||
| 78 | #define SMC_SYSCON_MSG_ARG_0 0x80000068 | ||
| 79 | |||
| 80 | #define SMC_PC_C 0x80000370 | ||
| 81 | |||
| 82 | #define SMC_SCRATCH9 0x80000424 | ||
| 83 | |||
| 84 | #define RCU_UC_EVENTS 0xC0000004 | ||
| 85 | # define BOOT_SEQ_DONE (1 << 7) | ||
| 86 | |||
| 32 | #define GENERAL_PWRMGT 0xC0200000 | 87 | #define GENERAL_PWRMGT 0xC0200000 |
| 88 | # define GLOBAL_PWRMGT_EN (1 << 0) | ||
| 89 | # define STATIC_PM_EN (1 << 1) | ||
| 90 | # define THERMAL_PROTECTION_DIS (1 << 2) | ||
| 91 | # define THERMAL_PROTECTION_TYPE (1 << 3) | ||
| 92 | # define SW_SMIO_INDEX(x) ((x) << 6) | ||
| 93 | # define SW_SMIO_INDEX_MASK (1 << 6) | ||
| 94 | # define SW_SMIO_INDEX_SHIFT 6 | ||
| 95 | # define VOLT_PWRMGT_EN (1 << 10) | ||
| 33 | # define GPU_COUNTER_CLK (1 << 15) | 96 | # define GPU_COUNTER_CLK (1 << 15) |
| 34 | 97 | # define DYN_SPREAD_SPECTRUM_EN (1 << 23) | |
| 98 | |||
| 99 | #define CNB_PWRMGT_CNTL 0xC0200004 | ||
| 100 | # define GNB_SLOW_MODE(x) ((x) << 0) | ||
| 101 | # define GNB_SLOW_MODE_MASK (3 << 0) | ||
| 102 | # define GNB_SLOW_MODE_SHIFT 0 | ||
| 103 | # define GNB_SLOW (1 << 2) | ||
| 104 | # define FORCE_NB_PS1 (1 << 3) | ||
| 105 | # define DPM_ENABLED (1 << 4) | ||
| 106 | |||
| 107 | #define SCLK_PWRMGT_CNTL 0xC0200008 | ||
| 108 | # define SCLK_PWRMGT_OFF (1 << 0) | ||
| 109 | # define RESET_BUSY_CNT (1 << 4) | ||
| 110 | # define RESET_SCLK_CNT (1 << 5) | ||
| 111 | # define DYNAMIC_PM_EN (1 << 21) | ||
| 112 | |||
| 113 | #define TARGET_AND_CURRENT_PROFILE_INDEX 0xC0200014 | ||
| 114 | # define CURRENT_STATE_MASK (0xf << 4) | ||
| 115 | # define CURRENT_STATE_SHIFT 4 | ||
| 116 | # define CURR_MCLK_INDEX_MASK (0xf << 8) | ||
| 117 | # define CURR_MCLK_INDEX_SHIFT 8 | ||
| 118 | # define CURR_SCLK_INDEX_MASK (0x1f << 16) | ||
| 119 | # define CURR_SCLK_INDEX_SHIFT 16 | ||
| 120 | |||
| 121 | #define CG_SSP 0xC0200044 | ||
| 122 | # define SST(x) ((x) << 0) | ||
| 123 | # define SST_MASK (0xffff << 0) | ||
| 124 | # define SSTU(x) ((x) << 16) | ||
| 125 | # define SSTU_MASK (0xf << 16) | ||
| 126 | |||
| 127 | #define CG_DISPLAY_GAP_CNTL 0xC0200060 | ||
| 128 | # define DISP_GAP(x) ((x) << 0) | ||
| 129 | # define DISP_GAP_MASK (3 << 0) | ||
| 130 | # define VBI_TIMER_COUNT(x) ((x) << 4) | ||
| 131 | # define VBI_TIMER_COUNT_MASK (0x3fff << 4) | ||
| 132 | # define VBI_TIMER_UNIT(x) ((x) << 20) | ||
| 133 | # define VBI_TIMER_UNIT_MASK (7 << 20) | ||
| 134 | # define DISP_GAP_MCHG(x) ((x) << 24) | ||
| 135 | # define DISP_GAP_MCHG_MASK (3 << 24) | ||
| 136 | |||
| 137 | #define SMU_VOLTAGE_STATUS 0xC0200094 | ||
| 138 | # define SMU_VOLTAGE_CURRENT_LEVEL_MASK (0xff << 1) | ||
| 139 | # define SMU_VOLTAGE_CURRENT_LEVEL_SHIFT 1 | ||
| 140 | |||
| 141 | #define TARGET_AND_CURRENT_PROFILE_INDEX_1 0xC02000F0 | ||
| 142 | # define CURR_PCIE_INDEX_MASK (0xf << 24) | ||
| 143 | # define CURR_PCIE_INDEX_SHIFT 24 | ||
| 144 | |||
| 145 | #define CG_ULV_PARAMETER 0xC0200158 | ||
| 146 | |||
| 147 | #define CG_FTV_0 0xC02001A8 | ||
| 148 | #define CG_FTV_1 0xC02001AC | ||
| 149 | #define CG_FTV_2 0xC02001B0 | ||
| 150 | #define CG_FTV_3 0xC02001B4 | ||
| 151 | #define CG_FTV_4 0xC02001B8 | ||
| 152 | #define CG_FTV_5 0xC02001BC | ||
| 153 | #define CG_FTV_6 0xC02001C0 | ||
| 154 | #define CG_FTV_7 0xC02001C4 | ||
| 155 | |||
| 156 | #define CG_DISPLAY_GAP_CNTL2 0xC0200230 | ||
| 157 | |||
| 158 | #define LCAC_SX0_OVR_SEL 0xC0400D04 | ||
| 159 | #define LCAC_SX0_OVR_VAL 0xC0400D08 | ||
| 160 | |||
| 161 | #define LCAC_MC0_CNTL 0xC0400D30 | ||
| 162 | #define LCAC_MC0_OVR_SEL 0xC0400D34 | ||
| 163 | #define LCAC_MC0_OVR_VAL 0xC0400D38 | ||
| 164 | #define LCAC_MC1_CNTL 0xC0400D3C | ||
| 165 | #define LCAC_MC1_OVR_SEL 0xC0400D40 | ||
| 166 | #define LCAC_MC1_OVR_VAL 0xC0400D44 | ||
| 167 | |||
| 168 | #define LCAC_MC2_OVR_SEL 0xC0400D4C | ||
| 169 | #define LCAC_MC2_OVR_VAL 0xC0400D50 | ||
| 170 | |||
| 171 | #define LCAC_MC3_OVR_SEL 0xC0400D58 | ||
| 172 | #define LCAC_MC3_OVR_VAL 0xC0400D5C | ||
| 173 | |||
| 174 | #define LCAC_CPL_CNTL 0xC0400D80 | ||
| 175 | #define LCAC_CPL_OVR_SEL 0xC0400D84 | ||
| 176 | #define LCAC_CPL_OVR_VAL 0xC0400D88 | ||
| 177 | |||
| 178 | /* dGPU */ | ||
| 179 | #define CG_THERMAL_CTRL 0xC0300004 | ||
| 180 | #define DPM_EVENT_SRC(x) ((x) << 0) | ||
| 181 | #define DPM_EVENT_SRC_MASK (7 << 0) | ||
| 182 | #define DIG_THERM_DPM(x) ((x) << 14) | ||
| 183 | #define DIG_THERM_DPM_MASK 0x003FC000 | ||
| 184 | #define DIG_THERM_DPM_SHIFT 14 | ||
| 185 | |||
| 186 | #define CG_THERMAL_INT 0xC030000C | ||
| 187 | #define CI_DIG_THERM_INTH(x) ((x) << 8) | ||
| 188 | #define CI_DIG_THERM_INTH_MASK 0x0000FF00 | ||
| 189 | #define CI_DIG_THERM_INTH_SHIFT 8 | ||
| 190 | #define CI_DIG_THERM_INTL(x) ((x) << 16) | ||
| 191 | #define CI_DIG_THERM_INTL_MASK 0x00FF0000 | ||
| 192 | #define CI_DIG_THERM_INTL_SHIFT 16 | ||
| 193 | #define THERM_INT_MASK_HIGH (1 << 24) | ||
| 194 | #define THERM_INT_MASK_LOW (1 << 25) | ||
| 195 | |||
| 196 | #define CG_MULT_THERMAL_STATUS 0xC0300014 | ||
| 197 | #define ASIC_MAX_TEMP(x) ((x) << 0) | ||
| 198 | #define ASIC_MAX_TEMP_MASK 0x000001ff | ||
| 199 | #define ASIC_MAX_TEMP_SHIFT 0 | ||
| 200 | #define CTF_TEMP(x) ((x) << 9) | ||
| 201 | #define CTF_TEMP_MASK 0x0003fe00 | ||
| 202 | #define CTF_TEMP_SHIFT 9 | ||
| 203 | |||
| 204 | #define CG_SPLL_FUNC_CNTL 0xC0500140 | ||
| 205 | #define SPLL_RESET (1 << 0) | ||
| 206 | #define SPLL_PWRON (1 << 1) | ||
| 207 | #define SPLL_BYPASS_EN (1 << 3) | ||
| 208 | #define SPLL_REF_DIV(x) ((x) << 5) | ||
| 209 | #define SPLL_REF_DIV_MASK (0x3f << 5) | ||
| 210 | #define SPLL_PDIV_A(x) ((x) << 20) | ||
| 211 | #define SPLL_PDIV_A_MASK (0x7f << 20) | ||
| 212 | #define SPLL_PDIV_A_SHIFT 20 | ||
| 213 | #define CG_SPLL_FUNC_CNTL_2 0xC0500144 | ||
| 214 | #define SCLK_MUX_SEL(x) ((x) << 0) | ||
| 215 | #define SCLK_MUX_SEL_MASK (0x1ff << 0) | ||
| 216 | #define CG_SPLL_FUNC_CNTL_3 0xC0500148 | ||
| 217 | #define SPLL_FB_DIV(x) ((x) << 0) | ||
| 218 | #define SPLL_FB_DIV_MASK (0x3ffffff << 0) | ||
| 219 | #define SPLL_FB_DIV_SHIFT 0 | ||
| 220 | #define SPLL_DITHEN (1 << 28) | ||
| 221 | #define CG_SPLL_FUNC_CNTL_4 0xC050014C | ||
| 222 | |||
| 223 | #define CG_SPLL_SPREAD_SPECTRUM 0xC0500164 | ||
| 224 | #define SSEN (1 << 0) | ||
| 225 | #define CLK_S(x) ((x) << 4) | ||
| 226 | #define CLK_S_MASK (0xfff << 4) | ||
| 227 | #define CLK_S_SHIFT 4 | ||
| 228 | #define CG_SPLL_SPREAD_SPECTRUM_2 0xC0500168 | ||
| 229 | #define CLK_V(x) ((x) << 0) | ||
| 230 | #define CLK_V_MASK (0x3ffffff << 0) | ||
| 231 | #define CLK_V_SHIFT 0 | ||
| 232 | |||
| 233 | #define MPLL_BYPASSCLK_SEL 0xC050019C | ||
| 234 | # define MPLL_CLKOUT_SEL(x) ((x) << 8) | ||
| 235 | # define MPLL_CLKOUT_SEL_MASK 0xFF00 | ||
| 35 | #define CG_CLKPIN_CNTL 0xC05001A0 | 236 | #define CG_CLKPIN_CNTL 0xC05001A0 |
| 36 | # define XTALIN_DIVIDE (1 << 1) | 237 | # define XTALIN_DIVIDE (1 << 1) |
| 37 | 238 | # define BCLK_AS_XCLK (1 << 2) | |
| 239 | #define CG_CLKPIN_CNTL_2 0xC05001A4 | ||
| 240 | # define FORCE_BIF_REFCLK_EN (1 << 3) | ||
| 241 | # define MUX_TCLK_TO_XCLK (1 << 8) | ||
| 242 | #define THM_CLK_CNTL 0xC05001A8 | ||
| 243 | # define CMON_CLK_SEL(x) ((x) << 0) | ||
| 244 | # define CMON_CLK_SEL_MASK 0xFF | ||
| 245 | # define TMON_CLK_SEL(x) ((x) << 8) | ||
| 246 | # define TMON_CLK_SEL_MASK 0xFF00 | ||
| 247 | #define MISC_CLK_CTRL 0xC05001AC | ||
| 248 | # define DEEP_SLEEP_CLK_SEL(x) ((x) << 0) | ||
| 249 | # define DEEP_SLEEP_CLK_SEL_MASK 0xFF | ||
| 250 | # define ZCLK_SEL(x) ((x) << 8) | ||
| 251 | # define ZCLK_SEL_MASK 0xFF00 | ||
| 252 | |||
| 253 | /* KV/KB */ | ||
| 254 | #define CG_THERMAL_INT_CTRL 0xC2100028 | ||
| 255 | #define DIG_THERM_INTH(x) ((x) << 0) | ||
| 256 | #define DIG_THERM_INTH_MASK 0x000000FF | ||
| 257 | #define DIG_THERM_INTH_SHIFT 0 | ||
| 258 | #define DIG_THERM_INTL(x) ((x) << 8) | ||
| 259 | #define DIG_THERM_INTL_MASK 0x0000FF00 | ||
| 260 | #define DIG_THERM_INTL_SHIFT 8 | ||
| 261 | #define THERM_INTH_MASK (1 << 24) | ||
| 262 | #define THERM_INTL_MASK (1 << 25) | ||
| 263 | |||
| 264 | /* PCIE registers idx/data 0x38/0x3c */ | ||
| 265 | #define PB0_PIF_PWRDOWN_0 0x1100012 /* PCIE */ | ||
| 266 | # define PLL_POWER_STATE_IN_TXS2_0(x) ((x) << 7) | ||
| 267 | # define PLL_POWER_STATE_IN_TXS2_0_MASK (0x7 << 7) | ||
| 268 | # define PLL_POWER_STATE_IN_TXS2_0_SHIFT 7 | ||
| 269 | # define PLL_POWER_STATE_IN_OFF_0(x) ((x) << 10) | ||
| 270 | # define PLL_POWER_STATE_IN_OFF_0_MASK (0x7 << 10) | ||
| 271 | # define PLL_POWER_STATE_IN_OFF_0_SHIFT 10 | ||
| 272 | # define PLL_RAMP_UP_TIME_0(x) ((x) << 24) | ||
| 273 | # define PLL_RAMP_UP_TIME_0_MASK (0x7 << 24) | ||
| 274 | # define PLL_RAMP_UP_TIME_0_SHIFT 24 | ||
| 275 | #define PB0_PIF_PWRDOWN_1 0x1100013 /* PCIE */ | ||
| 276 | # define PLL_POWER_STATE_IN_TXS2_1(x) ((x) << 7) | ||
| 277 | # define PLL_POWER_STATE_IN_TXS2_1_MASK (0x7 << 7) | ||
| 278 | # define PLL_POWER_STATE_IN_TXS2_1_SHIFT 7 | ||
| 279 | # define PLL_POWER_STATE_IN_OFF_1(x) ((x) << 10) | ||
| 280 | # define PLL_POWER_STATE_IN_OFF_1_MASK (0x7 << 10) | ||
| 281 | # define PLL_POWER_STATE_IN_OFF_1_SHIFT 10 | ||
| 282 | # define PLL_RAMP_UP_TIME_1(x) ((x) << 24) | ||
| 283 | # define PLL_RAMP_UP_TIME_1_MASK (0x7 << 24) | ||
| 284 | # define PLL_RAMP_UP_TIME_1_SHIFT 24 | ||
| 285 | |||
| 286 | #define PCIE_CNTL2 0x1001001c /* PCIE */ | ||
| 287 | # define SLV_MEM_LS_EN (1 << 16) | ||
| 288 | # define SLV_MEM_AGGRESSIVE_LS_EN (1 << 17) | ||
| 289 | # define MST_MEM_LS_EN (1 << 18) | ||
| 290 | # define REPLAY_MEM_LS_EN (1 << 19) | ||
| 291 | |||
| 292 | #define PCIE_LC_STATUS1 0x1400028 /* PCIE */ | ||
| 293 | # define LC_REVERSE_RCVR (1 << 0) | ||
| 294 | # define LC_REVERSE_XMIT (1 << 1) | ||
| 295 | # define LC_OPERATING_LINK_WIDTH_MASK (0x7 << 2) | ||
| 296 | # define LC_OPERATING_LINK_WIDTH_SHIFT 2 | ||
| 297 | # define LC_DETECTED_LINK_WIDTH_MASK (0x7 << 5) | ||
| 298 | # define LC_DETECTED_LINK_WIDTH_SHIFT 5 | ||
| 299 | |||
| 300 | #define PCIE_P_CNTL 0x1400040 /* PCIE */ | ||
| 301 | # define P_IGNORE_EDB_ERR (1 << 6) | ||
| 302 | |||
| 303 | #define PB1_PIF_PWRDOWN_0 0x2100012 /* PCIE */ | ||
| 304 | #define PB1_PIF_PWRDOWN_1 0x2100013 /* PCIE */ | ||
| 305 | |||
| 306 | #define PCIE_LC_CNTL 0x100100A0 /* PCIE */ | ||
| 307 | # define LC_L0S_INACTIVITY(x) ((x) << 8) | ||
| 308 | # define LC_L0S_INACTIVITY_MASK (0xf << 8) | ||
| 309 | # define LC_L0S_INACTIVITY_SHIFT 8 | ||
| 310 | # define LC_L1_INACTIVITY(x) ((x) << 12) | ||
| 311 | # define LC_L1_INACTIVITY_MASK (0xf << 12) | ||
| 312 | # define LC_L1_INACTIVITY_SHIFT 12 | ||
| 313 | # define LC_PMI_TO_L1_DIS (1 << 16) | ||
| 314 | # define LC_ASPM_TO_L1_DIS (1 << 24) | ||
| 315 | |||
| 316 | #define PCIE_LC_LINK_WIDTH_CNTL 0x100100A2 /* PCIE */ | ||
| 317 | # define LC_LINK_WIDTH_SHIFT 0 | ||
| 318 | # define LC_LINK_WIDTH_MASK 0x7 | ||
| 319 | # define LC_LINK_WIDTH_X0 0 | ||
| 320 | # define LC_LINK_WIDTH_X1 1 | ||
| 321 | # define LC_LINK_WIDTH_X2 2 | ||
| 322 | # define LC_LINK_WIDTH_X4 3 | ||
| 323 | # define LC_LINK_WIDTH_X8 4 | ||
| 324 | # define LC_LINK_WIDTH_X16 6 | ||
| 325 | # define LC_LINK_WIDTH_RD_SHIFT 4 | ||
| 326 | # define LC_LINK_WIDTH_RD_MASK 0x70 | ||
| 327 | # define LC_RECONFIG_ARC_MISSING_ESCAPE (1 << 7) | ||
| 328 | # define LC_RECONFIG_NOW (1 << 8) | ||
| 329 | # define LC_RENEGOTIATION_SUPPORT (1 << 9) | ||
| 330 | # define LC_RENEGOTIATE_EN (1 << 10) | ||
| 331 | # define LC_SHORT_RECONFIG_EN (1 << 11) | ||
| 332 | # define LC_UPCONFIGURE_SUPPORT (1 << 12) | ||
| 333 | # define LC_UPCONFIGURE_DIS (1 << 13) | ||
| 334 | # define LC_DYN_LANES_PWR_STATE(x) ((x) << 21) | ||
| 335 | # define LC_DYN_LANES_PWR_STATE_MASK (0x3 << 21) | ||
| 336 | # define LC_DYN_LANES_PWR_STATE_SHIFT 21 | ||
| 337 | #define PCIE_LC_N_FTS_CNTL 0x100100a3 /* PCIE */ | ||
| 338 | # define LC_XMIT_N_FTS(x) ((x) << 0) | ||
| 339 | # define LC_XMIT_N_FTS_MASK (0xff << 0) | ||
| 340 | # define LC_XMIT_N_FTS_SHIFT 0 | ||
| 341 | # define LC_XMIT_N_FTS_OVERRIDE_EN (1 << 8) | ||
| 342 | # define LC_N_FTS_MASK (0xff << 24) | ||
| 343 | #define PCIE_LC_SPEED_CNTL 0x100100A4 /* PCIE */ | ||
| 344 | # define LC_GEN2_EN_STRAP (1 << 0) | ||
| 345 | # define LC_GEN3_EN_STRAP (1 << 1) | ||
| 346 | # define LC_TARGET_LINK_SPEED_OVERRIDE_EN (1 << 2) | ||
| 347 | # define LC_TARGET_LINK_SPEED_OVERRIDE_MASK (0x3 << 3) | ||
| 348 | # define LC_TARGET_LINK_SPEED_OVERRIDE_SHIFT 3 | ||
| 349 | # define LC_FORCE_EN_SW_SPEED_CHANGE (1 << 5) | ||
| 350 | # define LC_FORCE_DIS_SW_SPEED_CHANGE (1 << 6) | ||
| 351 | # define LC_FORCE_EN_HW_SPEED_CHANGE (1 << 7) | ||
| 352 | # define LC_FORCE_DIS_HW_SPEED_CHANGE (1 << 8) | ||
| 353 | # define LC_INITIATE_LINK_SPEED_CHANGE (1 << 9) | ||
| 354 | # define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK (0x3 << 10) | ||
| 355 | # define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT 10 | ||
| 356 | # define LC_CURRENT_DATA_RATE_MASK (0x3 << 13) /* 0/1/2 = gen1/2/3 */ | ||
| 357 | # define LC_CURRENT_DATA_RATE_SHIFT 13 | ||
| 358 | # define LC_CLR_FAILED_SPD_CHANGE_CNT (1 << 16) | ||
| 359 | # define LC_OTHER_SIDE_EVER_SENT_GEN2 (1 << 18) | ||
| 360 | # define LC_OTHER_SIDE_SUPPORTS_GEN2 (1 << 19) | ||
| 361 | # define LC_OTHER_SIDE_EVER_SENT_GEN3 (1 << 20) | ||
| 362 | # define LC_OTHER_SIDE_SUPPORTS_GEN3 (1 << 21) | ||
| 363 | |||
| 364 | #define PCIE_LC_CNTL2 0x100100B1 /* PCIE */ | ||
| 365 | # define LC_ALLOW_PDWN_IN_L1 (1 << 17) | ||
| 366 | # define LC_ALLOW_PDWN_IN_L23 (1 << 18) | ||
| 367 | |||
| 368 | #define PCIE_LC_CNTL3 0x100100B5 /* PCIE */ | ||
| 369 | # define LC_GO_TO_RECOVERY (1 << 30) | ||
| 370 | #define PCIE_LC_CNTL4 0x100100B6 /* PCIE */ | ||
| 371 | # define LC_REDO_EQ (1 << 5) | ||
| 372 | # define LC_SET_QUIESCE (1 << 13) | ||
| 373 | |||
| 374 | /* direct registers */ | ||
| 38 | #define PCIE_INDEX 0x38 | 375 | #define PCIE_INDEX 0x38 |
| 39 | #define PCIE_DATA 0x3C | 376 | #define PCIE_DATA 0x3C |
| 40 | 377 | ||
| 378 | #define SMC_IND_INDEX_0 0x200 | ||
| 379 | #define SMC_IND_DATA_0 0x204 | ||
| 380 | |||
| 381 | #define SMC_IND_ACCESS_CNTL 0x240 | ||
| 382 | #define AUTO_INCREMENT_IND_0 (1 << 0) | ||
| 383 | |||
| 384 | #define SMC_MESSAGE_0 0x250 | ||
| 385 | #define SMC_MSG_MASK 0xffff | ||
| 386 | #define SMC_RESP_0 0x254 | ||
| 387 | #define SMC_RESP_MASK 0xffff | ||
| 388 | |||
| 389 | #define SMC_MSG_ARG_0 0x290 | ||
| 390 | |||
| 41 | #define VGA_HDP_CONTROL 0x328 | 391 | #define VGA_HDP_CONTROL 0x328 |
| 42 | #define VGA_MEMORY_DISABLE (1 << 4) | 392 | #define VGA_MEMORY_DISABLE (1 << 4) |
| 43 | 393 | ||
| 44 | #define DMIF_ADDR_CALC 0xC00 | 394 | #define DMIF_ADDR_CALC 0xC00 |
| 45 | 395 | ||
| 396 | #define PIPE0_DMIF_BUFFER_CONTROL 0x0ca0 | ||
| 397 | # define DMIF_BUFFERS_ALLOCATED(x) ((x) << 0) | ||
| 398 | # define DMIF_BUFFERS_ALLOCATED_COMPLETED (1 << 4) | ||
| 399 | |||
| 46 | #define SRBM_GFX_CNTL 0xE44 | 400 | #define SRBM_GFX_CNTL 0xE44 |
| 47 | #define PIPEID(x) ((x) << 0) | 401 | #define PIPEID(x) ((x) << 0) |
| 48 | #define MEID(x) ((x) << 2) | 402 | #define MEID(x) ((x) << 2) |
| @@ -172,6 +526,10 @@ | |||
| 172 | #define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x157C | 526 | #define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x157C |
| 173 | #define VM_CONTEXT1_PAGE_TABLE_END_ADDR 0x1580 | 527 | #define VM_CONTEXT1_PAGE_TABLE_END_ADDR 0x1580 |
| 174 | 528 | ||
| 529 | #define VM_L2_CG 0x15c0 | ||
| 530 | #define MC_CG_ENABLE (1 << 18) | ||
| 531 | #define MC_LS_ENABLE (1 << 19) | ||
| 532 | |||
| 175 | #define MC_SHARED_CHMAP 0x2004 | 533 | #define MC_SHARED_CHMAP 0x2004 |
| 176 | #define NOOFCHAN_SHIFT 12 | 534 | #define NOOFCHAN_SHIFT 12 |
| 177 | #define NOOFCHAN_MASK 0x0000f000 | 535 | #define NOOFCHAN_MASK 0x0000f000 |
| @@ -201,6 +559,17 @@ | |||
| 201 | 559 | ||
| 202 | #define MC_SHARED_BLACKOUT_CNTL 0x20ac | 560 | #define MC_SHARED_BLACKOUT_CNTL 0x20ac |
| 203 | 561 | ||
| 562 | #define MC_HUB_MISC_HUB_CG 0x20b8 | ||
| 563 | #define MC_HUB_MISC_VM_CG 0x20bc | ||
| 564 | |||
| 565 | #define MC_HUB_MISC_SIP_CG 0x20c0 | ||
| 566 | |||
| 567 | #define MC_XPB_CLK_GAT 0x2478 | ||
| 568 | |||
| 569 | #define MC_CITF_MISC_RD_CG 0x2648 | ||
| 570 | #define MC_CITF_MISC_WR_CG 0x264c | ||
| 571 | #define MC_CITF_MISC_VM_CG 0x2650 | ||
| 572 | |||
| 204 | #define MC_ARB_RAMCFG 0x2760 | 573 | #define MC_ARB_RAMCFG 0x2760 |
| 205 | #define NOOFBANK_SHIFT 0 | 574 | #define NOOFBANK_SHIFT 0 |
| 206 | #define NOOFBANK_MASK 0x00000003 | 575 | #define NOOFBANK_MASK 0x00000003 |
| @@ -215,9 +584,37 @@ | |||
| 215 | #define NOOFGROUPS_SHIFT 12 | 584 | #define NOOFGROUPS_SHIFT 12 |
| 216 | #define NOOFGROUPS_MASK 0x00001000 | 585 | #define NOOFGROUPS_MASK 0x00001000 |
| 217 | 586 | ||
| 587 | #define MC_ARB_DRAM_TIMING 0x2774 | ||
| 588 | #define MC_ARB_DRAM_TIMING2 0x2778 | ||
| 589 | |||
| 590 | #define MC_ARB_BURST_TIME 0x2808 | ||
| 591 | #define STATE0(x) ((x) << 0) | ||
| 592 | #define STATE0_MASK (0x1f << 0) | ||
| 593 | #define STATE0_SHIFT 0 | ||
| 594 | #define STATE1(x) ((x) << 5) | ||
| 595 | #define STATE1_MASK (0x1f << 5) | ||
| 596 | #define STATE1_SHIFT 5 | ||
| 597 | #define STATE2(x) ((x) << 10) | ||
| 598 | #define STATE2_MASK (0x1f << 10) | ||
| 599 | #define STATE2_SHIFT 10 | ||
| 600 | #define STATE3(x) ((x) << 15) | ||
| 601 | #define STATE3_MASK (0x1f << 15) | ||
| 602 | #define STATE3_SHIFT 15 | ||
| 603 | |||
| 604 | #define MC_SEQ_RAS_TIMING 0x28a0 | ||
| 605 | #define MC_SEQ_CAS_TIMING 0x28a4 | ||
| 606 | #define MC_SEQ_MISC_TIMING 0x28a8 | ||
| 607 | #define MC_SEQ_MISC_TIMING2 0x28ac | ||
| 608 | #define MC_SEQ_PMG_TIMING 0x28b0 | ||
| 609 | #define MC_SEQ_RD_CTL_D0 0x28b4 | ||
| 610 | #define MC_SEQ_RD_CTL_D1 0x28b8 | ||
| 611 | #define MC_SEQ_WR_CTL_D0 0x28bc | ||
| 612 | #define MC_SEQ_WR_CTL_D1 0x28c0 | ||
| 613 | |||
| 218 | #define MC_SEQ_SUP_CNTL 0x28c8 | 614 | #define MC_SEQ_SUP_CNTL 0x28c8 |
| 219 | #define RUN_MASK (1 << 0) | 615 | #define RUN_MASK (1 << 0) |
| 220 | #define MC_SEQ_SUP_PGM 0x28cc | 616 | #define MC_SEQ_SUP_PGM 0x28cc |
| 617 | #define MC_PMG_AUTO_CMD 0x28d0 | ||
| 221 | 618 | ||
| 222 | #define MC_SEQ_TRAIN_WAKEUP_CNTL 0x28e8 | 619 | #define MC_SEQ_TRAIN_WAKEUP_CNTL 0x28e8 |
| 223 | #define TRAIN_DONE_D0 (1 << 30) | 620 | #define TRAIN_DONE_D0 (1 << 30) |
| @@ -226,10 +623,92 @@ | |||
| 226 | #define MC_IO_PAD_CNTL_D0 0x29d0 | 623 | #define MC_IO_PAD_CNTL_D0 0x29d0 |
| 227 | #define MEM_FALL_OUT_CMD (1 << 8) | 624 | #define MEM_FALL_OUT_CMD (1 << 8) |
| 228 | 625 | ||
| 626 | #define MC_SEQ_MISC0 0x2a00 | ||
| 627 | #define MC_SEQ_MISC0_VEN_ID_SHIFT 8 | ||
| 628 | #define MC_SEQ_MISC0_VEN_ID_MASK 0x00000f00 | ||
| 629 | #define MC_SEQ_MISC0_VEN_ID_VALUE 3 | ||
| 630 | #define MC_SEQ_MISC0_REV_ID_SHIFT 12 | ||
| 631 | #define MC_SEQ_MISC0_REV_ID_MASK 0x0000f000 | ||
| 632 | #define MC_SEQ_MISC0_REV_ID_VALUE 1 | ||
| 633 | #define MC_SEQ_MISC0_GDDR5_SHIFT 28 | ||
| 634 | #define MC_SEQ_MISC0_GDDR5_MASK 0xf0000000 | ||
| 635 | #define MC_SEQ_MISC0_GDDR5_VALUE 5 | ||
| 636 | #define MC_SEQ_MISC1 0x2a04 | ||
| 637 | #define MC_SEQ_RESERVE_M 0x2a08 | ||
| 638 | #define MC_PMG_CMD_EMRS 0x2a0c | ||
| 639 | |||
| 229 | #define MC_SEQ_IO_DEBUG_INDEX 0x2a44 | 640 | #define MC_SEQ_IO_DEBUG_INDEX 0x2a44 |
| 230 | #define MC_SEQ_IO_DEBUG_DATA 0x2a48 | 641 | #define MC_SEQ_IO_DEBUG_DATA 0x2a48 |
| 231 | 642 | ||
| 643 | #define MC_SEQ_MISC5 0x2a54 | ||
| 644 | #define MC_SEQ_MISC6 0x2a58 | ||
| 645 | |||
| 646 | #define MC_SEQ_MISC7 0x2a64 | ||
| 647 | |||
| 648 | #define MC_SEQ_RAS_TIMING_LP 0x2a6c | ||
| 649 | #define MC_SEQ_CAS_TIMING_LP 0x2a70 | ||
| 650 | #define MC_SEQ_MISC_TIMING_LP 0x2a74 | ||
| 651 | #define MC_SEQ_MISC_TIMING2_LP 0x2a78 | ||
| 652 | #define MC_SEQ_WR_CTL_D0_LP 0x2a7c | ||
| 653 | #define MC_SEQ_WR_CTL_D1_LP 0x2a80 | ||
| 654 | #define MC_SEQ_PMG_CMD_EMRS_LP 0x2a84 | ||
| 655 | #define MC_SEQ_PMG_CMD_MRS_LP 0x2a88 | ||
| 656 | |||
| 657 | #define MC_PMG_CMD_MRS 0x2aac | ||
| 658 | |||
| 659 | #define MC_SEQ_RD_CTL_D0_LP 0x2b1c | ||
| 660 | #define MC_SEQ_RD_CTL_D1_LP 0x2b20 | ||
| 661 | |||
| 662 | #define MC_PMG_CMD_MRS1 0x2b44 | ||
| 663 | #define MC_SEQ_PMG_CMD_MRS1_LP 0x2b48 | ||
| 664 | #define MC_SEQ_PMG_TIMING_LP 0x2b4c | ||
| 665 | |||
| 666 | #define MC_SEQ_WR_CTL_2 0x2b54 | ||
| 667 | #define MC_SEQ_WR_CTL_2_LP 0x2b58 | ||
| 668 | #define MC_PMG_CMD_MRS2 0x2b5c | ||
| 669 | #define MC_SEQ_PMG_CMD_MRS2_LP 0x2b60 | ||
| 670 | |||
| 671 | #define MCLK_PWRMGT_CNTL 0x2ba0 | ||
| 672 | # define DLL_SPEED(x) ((x) << 0) | ||
| 673 | # define DLL_SPEED_MASK (0x1f << 0) | ||
| 674 | # define DLL_READY (1 << 6) | ||
| 675 | # define MC_INT_CNTL (1 << 7) | ||
| 676 | # define MRDCK0_PDNB (1 << 8) | ||
| 677 | # define MRDCK1_PDNB (1 << 9) | ||
| 678 | # define MRDCK0_RESET (1 << 16) | ||
| 679 | # define MRDCK1_RESET (1 << 17) | ||
| 680 | # define DLL_READY_READ (1 << 24) | ||
| 681 | #define DLL_CNTL 0x2ba4 | ||
| 682 | # define MRDCK0_BYPASS (1 << 24) | ||
| 683 | # define MRDCK1_BYPASS (1 << 25) | ||
| 684 | |||
| 685 | #define MPLL_FUNC_CNTL 0x2bb4 | ||
| 686 | #define BWCTRL(x) ((x) << 20) | ||
| 687 | #define BWCTRL_MASK (0xff << 20) | ||
| 688 | #define MPLL_FUNC_CNTL_1 0x2bb8 | ||
| 689 | #define VCO_MODE(x) ((x) << 0) | ||
| 690 | #define VCO_MODE_MASK (3 << 0) | ||
| 691 | #define CLKFRAC(x) ((x) << 4) | ||
| 692 | #define CLKFRAC_MASK (0xfff << 4) | ||
| 693 | #define CLKF(x) ((x) << 16) | ||
| 694 | #define CLKF_MASK (0xfff << 16) | ||
| 695 | #define MPLL_FUNC_CNTL_2 0x2bbc | ||
| 696 | #define MPLL_AD_FUNC_CNTL 0x2bc0 | ||
| 697 | #define YCLK_POST_DIV(x) ((x) << 0) | ||
| 698 | #define YCLK_POST_DIV_MASK (7 << 0) | ||
| 699 | #define MPLL_DQ_FUNC_CNTL 0x2bc4 | ||
| 700 | #define YCLK_SEL(x) ((x) << 4) | ||
| 701 | #define YCLK_SEL_MASK (1 << 4) | ||
| 702 | |||
| 703 | #define MPLL_SS1 0x2bcc | ||
| 704 | #define CLKV(x) ((x) << 0) | ||
| 705 | #define CLKV_MASK (0x3ffffff << 0) | ||
| 706 | #define MPLL_SS2 0x2bd0 | ||
| 707 | #define CLKS(x) ((x) << 0) | ||
| 708 | #define CLKS_MASK (0xfff << 0) | ||
| 709 | |||
| 232 | #define HDP_HOST_PATH_CNTL 0x2C00 | 710 | #define HDP_HOST_PATH_CNTL 0x2C00 |
| 711 | #define CLOCK_GATING_DIS (1 << 23) | ||
| 233 | #define HDP_NONSURFACE_BASE 0x2C04 | 712 | #define HDP_NONSURFACE_BASE 0x2C04 |
| 234 | #define HDP_NONSURFACE_INFO 0x2C08 | 713 | #define HDP_NONSURFACE_INFO 0x2C08 |
| 235 | #define HDP_NONSURFACE_SIZE 0x2C0C | 714 | #define HDP_NONSURFACE_SIZE 0x2C0C |
| @@ -237,6 +716,26 @@ | |||
| 237 | #define HDP_ADDR_CONFIG 0x2F48 | 716 | #define HDP_ADDR_CONFIG 0x2F48 |
| 238 | #define HDP_MISC_CNTL 0x2F4C | 717 | #define HDP_MISC_CNTL 0x2F4C |
| 239 | #define HDP_FLUSH_INVALIDATE_CACHE (1 << 0) | 718 | #define HDP_FLUSH_INVALIDATE_CACHE (1 << 0) |
| 719 | #define HDP_MEM_POWER_LS 0x2F50 | ||
| 720 | #define HDP_LS_ENABLE (1 << 0) | ||
| 721 | |||
| 722 | #define ATC_MISC_CG 0x3350 | ||
| 723 | |||
| 724 | #define MC_SEQ_CNTL_3 0x3600 | ||
| 725 | # define CAC_EN (1 << 31) | ||
| 726 | #define MC_SEQ_G5PDX_CTRL 0x3604 | ||
| 727 | #define MC_SEQ_G5PDX_CTRL_LP 0x3608 | ||
| 728 | #define MC_SEQ_G5PDX_CMD0 0x360c | ||
| 729 | #define MC_SEQ_G5PDX_CMD0_LP 0x3610 | ||
| 730 | #define MC_SEQ_G5PDX_CMD1 0x3614 | ||
| 731 | #define MC_SEQ_G5PDX_CMD1_LP 0x3618 | ||
| 732 | |||
| 733 | #define MC_SEQ_PMG_DVS_CTL 0x3628 | ||
| 734 | #define MC_SEQ_PMG_DVS_CTL_LP 0x362c | ||
| 735 | #define MC_SEQ_PMG_DVS_CMD 0x3630 | ||
| 736 | #define MC_SEQ_PMG_DVS_CMD_LP 0x3634 | ||
| 737 | #define MC_SEQ_DLL_STBY 0x3638 | ||
| 738 | #define MC_SEQ_DLL_STBY_LP 0x363c | ||
| 240 | 739 | ||
| 241 | #define IH_RB_CNTL 0x3e00 | 740 | #define IH_RB_CNTL 0x3e00 |
| 242 | # define IH_RB_ENABLE (1 << 0) | 741 | # define IH_RB_ENABLE (1 << 0) |
| @@ -265,6 +764,9 @@ | |||
| 265 | # define MC_WR_CLEAN_CNT(x) ((x) << 20) | 764 | # define MC_WR_CLEAN_CNT(x) ((x) << 20) |
| 266 | # define MC_VMID(x) ((x) << 25) | 765 | # define MC_VMID(x) ((x) << 25) |
| 267 | 766 | ||
| 767 | #define BIF_LNCNT_RESET 0x5220 | ||
| 768 | # define RESET_LNCNT_EN (1 << 0) | ||
| 769 | |||
| 268 | #define CONFIG_MEMSIZE 0x5428 | 770 | #define CONFIG_MEMSIZE 0x5428 |
| 269 | 771 | ||
| 270 | #define INTERRUPT_CNTL 0x5468 | 772 | #define INTERRUPT_CNTL 0x5468 |
| @@ -401,6 +903,9 @@ | |||
| 401 | # define DC_HPDx_RX_INT_TIMER(x) ((x) << 16) | 903 | # define DC_HPDx_RX_INT_TIMER(x) ((x) << 16) |
| 402 | # define DC_HPDx_EN (1 << 28) | 904 | # define DC_HPDx_EN (1 << 28) |
| 403 | 905 | ||
| 906 | #define DPG_PIPE_STUTTER_CONTROL 0x6cd4 | ||
| 907 | # define STUTTER_ENABLE (1 << 0) | ||
| 908 | |||
| 404 | #define GRBM_CNTL 0x8000 | 909 | #define GRBM_CNTL 0x8000 |
| 405 | #define GRBM_READ_TIMEOUT(x) ((x) << 0) | 910 | #define GRBM_READ_TIMEOUT(x) ((x) << 0) |
| 406 | 911 | ||
| @@ -504,6 +1009,9 @@ | |||
| 504 | 1009 | ||
| 505 | #define CP_RB0_RPTR 0x8700 | 1010 | #define CP_RB0_RPTR 0x8700 |
| 506 | #define CP_RB_WPTR_DELAY 0x8704 | 1011 | #define CP_RB_WPTR_DELAY 0x8704 |
| 1012 | #define CP_RB_WPTR_POLL_CNTL 0x8708 | ||
| 1013 | #define IDLE_POLL_COUNT(x) ((x) << 16) | ||
| 1014 | #define IDLE_POLL_COUNT_MASK (0xffff << 16) | ||
| 507 | 1015 | ||
| 508 | #define CP_MEQ_THRESHOLDS 0x8764 | 1016 | #define CP_MEQ_THRESHOLDS 0x8764 |
| 509 | #define MEQ1_START(x) ((x) << 0) | 1017 | #define MEQ1_START(x) ((x) << 0) |
| @@ -730,6 +1238,9 @@ | |||
| 730 | # define CP_RINGID1_INT_STAT (1 << 30) | 1238 | # define CP_RINGID1_INT_STAT (1 << 30) |
| 731 | # define CP_RINGID0_INT_STAT (1 << 31) | 1239 | # define CP_RINGID0_INT_STAT (1 << 31) |
| 732 | 1240 | ||
| 1241 | #define CP_MEM_SLP_CNTL 0xC1E4 | ||
| 1242 | # define CP_MEM_LS_EN (1 << 0) | ||
| 1243 | |||
| 733 | #define CP_CPF_DEBUG 0xC200 | 1244 | #define CP_CPF_DEBUG 0xC200 |
| 734 | 1245 | ||
| 735 | #define CP_PQ_WPTR_POLL_CNTL 0xC20C | 1246 | #define CP_PQ_WPTR_POLL_CNTL 0xC20C |
| @@ -775,14 +1286,20 @@ | |||
| 775 | 1286 | ||
| 776 | #define RLC_MC_CNTL 0xC30C | 1287 | #define RLC_MC_CNTL 0xC30C |
| 777 | 1288 | ||
| 1289 | #define RLC_MEM_SLP_CNTL 0xC318 | ||
| 1290 | # define RLC_MEM_LS_EN (1 << 0) | ||
| 1291 | |||
| 778 | #define RLC_LB_CNTR_MAX 0xC348 | 1292 | #define RLC_LB_CNTR_MAX 0xC348 |
| 779 | 1293 | ||
| 780 | #define RLC_LB_CNTL 0xC364 | 1294 | #define RLC_LB_CNTL 0xC364 |
| 1295 | # define LOAD_BALANCE_ENABLE (1 << 0) | ||
| 781 | 1296 | ||
| 782 | #define RLC_LB_CNTR_INIT 0xC36C | 1297 | #define RLC_LB_CNTR_INIT 0xC36C |
| 783 | 1298 | ||
| 784 | #define RLC_SAVE_AND_RESTORE_BASE 0xC374 | 1299 | #define RLC_SAVE_AND_RESTORE_BASE 0xC374 |
| 785 | #define RLC_DRIVER_DMA_STATUS 0xC378 | 1300 | #define RLC_DRIVER_DMA_STATUS 0xC378 /* dGPU */ |
| 1301 | #define RLC_CP_TABLE_RESTORE 0xC378 /* APU */ | ||
| 1302 | #define RLC_PG_DELAY_2 0xC37C | ||
| 786 | 1303 | ||
| 787 | #define RLC_GPM_UCODE_ADDR 0xC388 | 1304 | #define RLC_GPM_UCODE_ADDR 0xC388 |
| 788 | #define RLC_GPM_UCODE_DATA 0xC38C | 1305 | #define RLC_GPM_UCODE_DATA 0xC38C |
| @@ -791,12 +1308,52 @@ | |||
| 791 | #define RLC_CAPTURE_GPU_CLOCK_COUNT 0xC398 | 1308 | #define RLC_CAPTURE_GPU_CLOCK_COUNT 0xC398 |
| 792 | #define RLC_UCODE_CNTL 0xC39C | 1309 | #define RLC_UCODE_CNTL 0xC39C |
| 793 | 1310 | ||
| 1311 | #define RLC_GPM_STAT 0xC400 | ||
| 1312 | # define RLC_GPM_BUSY (1 << 0) | ||
| 1313 | # define GFX_POWER_STATUS (1 << 1) | ||
| 1314 | # define GFX_CLOCK_STATUS (1 << 2) | ||
| 1315 | |||
| 1316 | #define RLC_PG_CNTL 0xC40C | ||
| 1317 | # define GFX_PG_ENABLE (1 << 0) | ||
| 1318 | # define GFX_PG_SRC (1 << 1) | ||
| 1319 | # define DYN_PER_CU_PG_ENABLE (1 << 2) | ||
| 1320 | # define STATIC_PER_CU_PG_ENABLE (1 << 3) | ||
| 1321 | # define DISABLE_GDS_PG (1 << 13) | ||
| 1322 | # define DISABLE_CP_PG (1 << 15) | ||
| 1323 | # define SMU_CLK_SLOWDOWN_ON_PU_ENABLE (1 << 17) | ||
| 1324 | # define SMU_CLK_SLOWDOWN_ON_PD_ENABLE (1 << 18) | ||
| 1325 | |||
| 1326 | #define RLC_CGTT_MGCG_OVERRIDE 0xC420 | ||
| 794 | #define RLC_CGCG_CGLS_CTRL 0xC424 | 1327 | #define RLC_CGCG_CGLS_CTRL 0xC424 |
| 1328 | # define CGCG_EN (1 << 0) | ||
| 1329 | # define CGLS_EN (1 << 1) | ||
| 1330 | |||
| 1331 | #define RLC_PG_DELAY 0xC434 | ||
| 795 | 1332 | ||
| 796 | #define RLC_LB_INIT_CU_MASK 0xC43C | 1333 | #define RLC_LB_INIT_CU_MASK 0xC43C |
| 797 | 1334 | ||
| 798 | #define RLC_LB_PARAMS 0xC444 | 1335 | #define RLC_LB_PARAMS 0xC444 |
| 799 | 1336 | ||
| 1337 | #define RLC_PG_AO_CU_MASK 0xC44C | ||
| 1338 | |||
| 1339 | #define RLC_MAX_PG_CU 0xC450 | ||
| 1340 | # define MAX_PU_CU(x) ((x) << 0) | ||
| 1341 | # define MAX_PU_CU_MASK (0xff << 0) | ||
| 1342 | #define RLC_AUTO_PG_CTRL 0xC454 | ||
| 1343 | # define AUTO_PG_EN (1 << 0) | ||
| 1344 | # define GRBM_REG_SGIT(x) ((x) << 3) | ||
| 1345 | # define GRBM_REG_SGIT_MASK (0xffff << 3) | ||
| 1346 | |||
| 1347 | #define RLC_SERDES_WR_CU_MASTER_MASK 0xC474 | ||
| 1348 | #define RLC_SERDES_WR_NONCU_MASTER_MASK 0xC478 | ||
| 1349 | #define RLC_SERDES_WR_CTRL 0xC47C | ||
| 1350 | #define BPM_ADDR(x) ((x) << 0) | ||
| 1351 | #define BPM_ADDR_MASK (0xff << 0) | ||
| 1352 | #define CGLS_ENABLE (1 << 16) | ||
| 1353 | #define CGCG_OVERRIDE_0 (1 << 20) | ||
| 1354 | #define MGCG_OVERRIDE_0 (1 << 22) | ||
| 1355 | #define MGCG_OVERRIDE_1 (1 << 23) | ||
| 1356 | |||
| 800 | #define RLC_SERDES_CU_MASTER_BUSY 0xC484 | 1357 | #define RLC_SERDES_CU_MASTER_BUSY 0xC484 |
| 801 | #define RLC_SERDES_NONCU_MASTER_BUSY 0xC488 | 1358 | #define RLC_SERDES_NONCU_MASTER_BUSY 0xC488 |
| 802 | # define SE_MASTER_BUSY_MASK 0x0000ffff | 1359 | # define SE_MASTER_BUSY_MASK 0x0000ffff |
| @@ -807,6 +1364,13 @@ | |||
| 807 | #define RLC_GPM_SCRATCH_ADDR 0xC4B0 | 1364 | #define RLC_GPM_SCRATCH_ADDR 0xC4B0 |
| 808 | #define RLC_GPM_SCRATCH_DATA 0xC4B4 | 1365 | #define RLC_GPM_SCRATCH_DATA 0xC4B4 |
| 809 | 1366 | ||
| 1367 | #define RLC_GPR_REG2 0xC4E8 | ||
| 1368 | #define REQ 0x00000001 | ||
| 1369 | #define MESSAGE(x) ((x) << 1) | ||
| 1370 | #define MESSAGE_MASK 0x0000001e | ||
| 1371 | #define MSG_ENTER_RLC_SAFE_MODE 1 | ||
| 1372 | #define MSG_EXIT_RLC_SAFE_MODE 0 | ||
| 1373 | |||
| 810 | #define CP_HPD_EOP_BASE_ADDR 0xC904 | 1374 | #define CP_HPD_EOP_BASE_ADDR 0xC904 |
| 811 | #define CP_HPD_EOP_BASE_ADDR_HI 0xC908 | 1375 | #define CP_HPD_EOP_BASE_ADDR_HI 0xC908 |
| 812 | #define CP_HPD_EOP_VMID 0xC90C | 1376 | #define CP_HPD_EOP_VMID 0xC90C |
| @@ -851,6 +1415,8 @@ | |||
| 851 | #define MQD_VMID(x) ((x) << 0) | 1415 | #define MQD_VMID(x) ((x) << 0) |
| 852 | #define MQD_VMID_MASK (0xf << 0) | 1416 | #define MQD_VMID_MASK (0xf << 0) |
| 853 | 1417 | ||
| 1418 | #define DB_RENDER_CONTROL 0x28000 | ||
| 1419 | |||
| 854 | #define PA_SC_RASTER_CONFIG 0x28350 | 1420 | #define PA_SC_RASTER_CONFIG 0x28350 |
| 855 | # define RASTER_CONFIG_RB_MAP_0 0 | 1421 | # define RASTER_CONFIG_RB_MAP_0 0 |
| 856 | # define RASTER_CONFIG_RB_MAP_1 1 | 1422 | # define RASTER_CONFIG_RB_MAP_1 1 |
| @@ -944,6 +1510,16 @@ | |||
| 944 | 1510 | ||
| 945 | #define CP_PERFMON_CNTL 0x36020 | 1511 | #define CP_PERFMON_CNTL 0x36020 |
| 946 | 1512 | ||
| 1513 | #define CGTS_SM_CTRL_REG 0x3c000 | ||
| 1514 | #define SM_MODE(x) ((x) << 17) | ||
| 1515 | #define SM_MODE_MASK (0x7 << 17) | ||
| 1516 | #define SM_MODE_ENABLE (1 << 20) | ||
| 1517 | #define CGTS_OVERRIDE (1 << 21) | ||
| 1518 | #define CGTS_LS_OVERRIDE (1 << 22) | ||
| 1519 | #define ON_MONITOR_ADD_EN (1 << 23) | ||
| 1520 | #define ON_MONITOR_ADD(x) ((x) << 24) | ||
| 1521 | #define ON_MONITOR_ADD_MASK (0xff << 24) | ||
| 1522 | |||
| 947 | #define CGTS_TCC_DISABLE 0x3c00c | 1523 | #define CGTS_TCC_DISABLE 0x3c00c |
| 948 | #define CGTS_USER_TCC_DISABLE 0x3c010 | 1524 | #define CGTS_USER_TCC_DISABLE 0x3c010 |
| 949 | #define TCC_DISABLE_MASK 0xFFFF0000 | 1525 | #define TCC_DISABLE_MASK 0xFFFF0000 |
| @@ -1176,6 +1752,8 @@ | |||
| 1176 | 1752 | ||
| 1177 | #define SDMA0_UCODE_ADDR 0xD000 | 1753 | #define SDMA0_UCODE_ADDR 0xD000 |
| 1178 | #define SDMA0_UCODE_DATA 0xD004 | 1754 | #define SDMA0_UCODE_DATA 0xD004 |
| 1755 | #define SDMA0_POWER_CNTL 0xD008 | ||
| 1756 | #define SDMA0_CLK_CTRL 0xD00C | ||
| 1179 | 1757 | ||
| 1180 | #define SDMA0_CNTL 0xD010 | 1758 | #define SDMA0_CNTL 0xD010 |
| 1181 | # define TRAP_ENABLE (1 << 0) | 1759 | # define TRAP_ENABLE (1 << 0) |
| @@ -1300,6 +1878,13 @@ | |||
| 1300 | #define UVD_RBC_RB_RPTR 0xf690 | 1878 | #define UVD_RBC_RB_RPTR 0xf690 |
| 1301 | #define UVD_RBC_RB_WPTR 0xf694 | 1879 | #define UVD_RBC_RB_WPTR 0xf694 |
| 1302 | 1880 | ||
| 1881 | #define UVD_CGC_CTRL 0xF4B0 | ||
| 1882 | # define DCM (1 << 0) | ||
| 1883 | # define CG_DT(x) ((x) << 2) | ||
| 1884 | # define CG_DT_MASK (0xf << 2) | ||
| 1885 | # define CLK_OD(x) ((x) << 6) | ||
| 1886 | # define CLK_OD_MASK (0x1f << 6) | ||
| 1887 | |||
| 1303 | /* UVD clocks */ | 1888 | /* UVD clocks */ |
| 1304 | 1889 | ||
| 1305 | #define CG_DCLK_CNTL 0xC050009C | 1890 | #define CG_DCLK_CNTL 0xC050009C |
| @@ -1310,4 +1895,7 @@ | |||
| 1310 | #define CG_VCLK_CNTL 0xC05000A4 | 1895 | #define CG_VCLK_CNTL 0xC05000A4 |
| 1311 | #define CG_VCLK_STATUS 0xC05000A8 | 1896 | #define CG_VCLK_STATUS 0xC05000A8 |
| 1312 | 1897 | ||
| 1898 | /* UVD CTX indirect */ | ||
| 1899 | #define UVD_CGC_MEM_CTRL 0xC0 | ||
| 1900 | |||
| 1313 | #endif | 1901 | #endif |