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path: root/drivers/gpu/drm/radeon/cik_sdma.c
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Diffstat (limited to 'drivers/gpu/drm/radeon/cik_sdma.c')
-rw-r--r--drivers/gpu/drm/radeon/cik_sdma.c26
1 files changed, 13 insertions, 13 deletions
diff --git a/drivers/gpu/drm/radeon/cik_sdma.c b/drivers/gpu/drm/radeon/cik_sdma.c
index 1347162ca1a4..8e9d0f1d858e 100644
--- a/drivers/gpu/drm/radeon/cik_sdma.c
+++ b/drivers/gpu/drm/radeon/cik_sdma.c
@@ -141,7 +141,7 @@ void cik_sdma_ring_ib_execute(struct radeon_device *rdev,
141 next_rptr += 4; 141 next_rptr += 4;
142 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0)); 142 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0));
143 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc); 143 radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
144 radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xffffffff); 144 radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr));
145 radeon_ring_write(ring, 1); /* number of DWs to follow */ 145 radeon_ring_write(ring, 1); /* number of DWs to follow */
146 radeon_ring_write(ring, next_rptr); 146 radeon_ring_write(ring, next_rptr);
147 } 147 }
@@ -151,7 +151,7 @@ void cik_sdma_ring_ib_execute(struct radeon_device *rdev,
151 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0)); 151 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_NOP, 0, 0));
152 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_INDIRECT_BUFFER, 0, extra_bits)); 152 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_INDIRECT_BUFFER, 0, extra_bits));
153 radeon_ring_write(ring, ib->gpu_addr & 0xffffffe0); /* base must be 32 byte aligned */ 153 radeon_ring_write(ring, ib->gpu_addr & 0xffffffe0); /* base must be 32 byte aligned */
154 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xffffffff); 154 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr));
155 radeon_ring_write(ring, ib->length_dw); 155 radeon_ring_write(ring, ib->length_dw);
156 156
157} 157}
@@ -203,8 +203,8 @@ void cik_sdma_fence_ring_emit(struct radeon_device *rdev,
203 203
204 /* write the fence */ 204 /* write the fence */
205 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_FENCE, 0, 0)); 205 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_FENCE, 0, 0));
206 radeon_ring_write(ring, addr & 0xffffffff); 206 radeon_ring_write(ring, lower_32_bits(addr));
207 radeon_ring_write(ring, upper_32_bits(addr) & 0xffffffff); 207 radeon_ring_write(ring, upper_32_bits(addr));
208 radeon_ring_write(ring, fence->seq); 208 radeon_ring_write(ring, fence->seq);
209 /* generate an interrupt */ 209 /* generate an interrupt */
210 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_TRAP, 0, 0)); 210 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_TRAP, 0, 0));
@@ -233,7 +233,7 @@ bool cik_sdma_semaphore_ring_emit(struct radeon_device *rdev,
233 233
234 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SEMAPHORE, 0, extra_bits)); 234 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SEMAPHORE, 0, extra_bits));
235 radeon_ring_write(ring, addr & 0xfffffff8); 235 radeon_ring_write(ring, addr & 0xfffffff8);
236 radeon_ring_write(ring, upper_32_bits(addr) & 0xffffffff); 236 radeon_ring_write(ring, upper_32_bits(addr));
237 237
238 return true; 238 return true;
239} 239}
@@ -551,10 +551,10 @@ int cik_copy_dma(struct radeon_device *rdev,
551 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_COPY, SDMA_COPY_SUB_OPCODE_LINEAR, 0)); 551 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_COPY, SDMA_COPY_SUB_OPCODE_LINEAR, 0));
552 radeon_ring_write(ring, cur_size_in_bytes); 552 radeon_ring_write(ring, cur_size_in_bytes);
553 radeon_ring_write(ring, 0); /* src/dst endian swap */ 553 radeon_ring_write(ring, 0); /* src/dst endian swap */
554 radeon_ring_write(ring, src_offset & 0xffffffff); 554 radeon_ring_write(ring, lower_32_bits(src_offset));
555 radeon_ring_write(ring, upper_32_bits(src_offset) & 0xffffffff); 555 radeon_ring_write(ring, upper_32_bits(src_offset));
556 radeon_ring_write(ring, dst_offset & 0xffffffff); 556 radeon_ring_write(ring, lower_32_bits(dst_offset));
557 radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xffffffff); 557 radeon_ring_write(ring, upper_32_bits(dst_offset));
558 src_offset += cur_size_in_bytes; 558 src_offset += cur_size_in_bytes;
559 dst_offset += cur_size_in_bytes; 559 dst_offset += cur_size_in_bytes;
560 } 560 }
@@ -605,7 +605,7 @@ int cik_sdma_ring_test(struct radeon_device *rdev,
605 } 605 }
606 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0)); 606 radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0));
607 radeon_ring_write(ring, rdev->vram_scratch.gpu_addr & 0xfffffffc); 607 radeon_ring_write(ring, rdev->vram_scratch.gpu_addr & 0xfffffffc);
608 radeon_ring_write(ring, upper_32_bits(rdev->vram_scratch.gpu_addr) & 0xffffffff); 608 radeon_ring_write(ring, upper_32_bits(rdev->vram_scratch.gpu_addr));
609 radeon_ring_write(ring, 1); /* number of DWs to follow */ 609 radeon_ring_write(ring, 1); /* number of DWs to follow */
610 radeon_ring_write(ring, 0xDEADBEEF); 610 radeon_ring_write(ring, 0xDEADBEEF);
611 radeon_ring_unlock_commit(rdev, ring); 611 radeon_ring_unlock_commit(rdev, ring);
@@ -660,7 +660,7 @@ int cik_sdma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring)
660 660
661 ib.ptr[0] = SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0); 661 ib.ptr[0] = SDMA_PACKET(SDMA_OPCODE_WRITE, SDMA_WRITE_SUB_OPCODE_LINEAR, 0);
662 ib.ptr[1] = rdev->vram_scratch.gpu_addr & 0xfffffffc; 662 ib.ptr[1] = rdev->vram_scratch.gpu_addr & 0xfffffffc;
663 ib.ptr[2] = upper_32_bits(rdev->vram_scratch.gpu_addr) & 0xffffffff; 663 ib.ptr[2] = upper_32_bits(rdev->vram_scratch.gpu_addr);
664 ib.ptr[3] = 1; 664 ib.ptr[3] = 1;
665 ib.ptr[4] = 0xDEADBEEF; 665 ib.ptr[4] = 0xDEADBEEF;
666 ib.length_dw = 5; 666 ib.length_dw = 5;
@@ -752,9 +752,9 @@ void cik_sdma_vm_set_page(struct radeon_device *rdev,
752 ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_COPY, SDMA_WRITE_SUB_OPCODE_LINEAR, 0); 752 ib->ptr[ib->length_dw++] = SDMA_PACKET(SDMA_OPCODE_COPY, SDMA_WRITE_SUB_OPCODE_LINEAR, 0);
753 ib->ptr[ib->length_dw++] = bytes; 753 ib->ptr[ib->length_dw++] = bytes;
754 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */ 754 ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
755 ib->ptr[ib->length_dw++] = src & 0xffffffff; 755 ib->ptr[ib->length_dw++] = lower_32_bits(src);
756 ib->ptr[ib->length_dw++] = upper_32_bits(src); 756 ib->ptr[ib->length_dw++] = upper_32_bits(src);
757 ib->ptr[ib->length_dw++] = pe & 0xffffffff; 757 ib->ptr[ib->length_dw++] = lower_32_bits(pe);
758 ib->ptr[ib->length_dw++] = upper_32_bits(pe); 758 ib->ptr[ib->length_dw++] = upper_32_bits(pe);
759 759
760 pe += bytes; 760 pe += bytes;