diff options
Diffstat (limited to 'drivers/gpu/drm/radeon/cik_sdma.c')
| -rw-r--r-- | drivers/gpu/drm/radeon/cik_sdma.c | 42 |
1 files changed, 17 insertions, 25 deletions
diff --git a/drivers/gpu/drm/radeon/cik_sdma.c b/drivers/gpu/drm/radeon/cik_sdma.c index d748963af08b..dde5c7e29eb2 100644 --- a/drivers/gpu/drm/radeon/cik_sdma.c +++ b/drivers/gpu/drm/radeon/cik_sdma.c | |||
| @@ -134,7 +134,7 @@ void cik_sdma_ring_ib_execute(struct radeon_device *rdev, | |||
| 134 | struct radeon_ib *ib) | 134 | struct radeon_ib *ib) |
| 135 | { | 135 | { |
| 136 | struct radeon_ring *ring = &rdev->ring[ib->ring]; | 136 | struct radeon_ring *ring = &rdev->ring[ib->ring]; |
| 137 | u32 extra_bits = (ib->vm ? ib->vm->id : 0) & 0xf; | 137 | u32 extra_bits = (ib->vm ? ib->vm->ids[ib->ring].id : 0) & 0xf; |
| 138 | 138 | ||
| 139 | if (rdev->wb.enabled) { | 139 | if (rdev->wb.enabled) { |
| 140 | u32 next_rptr = ring->wptr + 5; | 140 | u32 next_rptr = ring->wptr + 5; |
| @@ -541,31 +541,27 @@ struct radeon_fence *cik_copy_dma(struct radeon_device *rdev, | |||
| 541 | unsigned num_gpu_pages, | 541 | unsigned num_gpu_pages, |
| 542 | struct reservation_object *resv) | 542 | struct reservation_object *resv) |
| 543 | { | 543 | { |
| 544 | struct radeon_semaphore *sem = NULL; | ||
| 545 | struct radeon_fence *fence; | 544 | struct radeon_fence *fence; |
| 545 | struct radeon_sync sync; | ||
| 546 | int ring_index = rdev->asic->copy.dma_ring_index; | 546 | int ring_index = rdev->asic->copy.dma_ring_index; |
| 547 | struct radeon_ring *ring = &rdev->ring[ring_index]; | 547 | struct radeon_ring *ring = &rdev->ring[ring_index]; |
| 548 | u32 size_in_bytes, cur_size_in_bytes; | 548 | u32 size_in_bytes, cur_size_in_bytes; |
| 549 | int i, num_loops; | 549 | int i, num_loops; |
| 550 | int r = 0; | 550 | int r = 0; |
| 551 | 551 | ||
| 552 | r = radeon_semaphore_create(rdev, &sem); | 552 | radeon_sync_create(&sync); |
| 553 | if (r) { | ||
| 554 | DRM_ERROR("radeon: moving bo (%d).\n", r); | ||
| 555 | return ERR_PTR(r); | ||
| 556 | } | ||
| 557 | 553 | ||
| 558 | size_in_bytes = (num_gpu_pages << RADEON_GPU_PAGE_SHIFT); | 554 | size_in_bytes = (num_gpu_pages << RADEON_GPU_PAGE_SHIFT); |
| 559 | num_loops = DIV_ROUND_UP(size_in_bytes, 0x1fffff); | 555 | num_loops = DIV_ROUND_UP(size_in_bytes, 0x1fffff); |
| 560 | r = radeon_ring_lock(rdev, ring, num_loops * 7 + 14); | 556 | r = radeon_ring_lock(rdev, ring, num_loops * 7 + 14); |
| 561 | if (r) { | 557 | if (r) { |
| 562 | DRM_ERROR("radeon: moving bo (%d).\n", r); | 558 | DRM_ERROR("radeon: moving bo (%d).\n", r); |
| 563 | radeon_semaphore_free(rdev, &sem, NULL); | 559 | radeon_sync_free(rdev, &sync, NULL); |
| 564 | return ERR_PTR(r); | 560 | return ERR_PTR(r); |
| 565 | } | 561 | } |
| 566 | 562 | ||
| 567 | radeon_semaphore_sync_resv(rdev, sem, resv, false); | 563 | radeon_sync_resv(rdev, &sync, resv, false); |
| 568 | radeon_semaphore_sync_rings(rdev, sem, ring->idx); | 564 | radeon_sync_rings(rdev, &sync, ring->idx); |
| 569 | 565 | ||
| 570 | for (i = 0; i < num_loops; i++) { | 566 | for (i = 0; i < num_loops; i++) { |
| 571 | cur_size_in_bytes = size_in_bytes; | 567 | cur_size_in_bytes = size_in_bytes; |
| @@ -586,12 +582,12 @@ struct radeon_fence *cik_copy_dma(struct radeon_device *rdev, | |||
| 586 | r = radeon_fence_emit(rdev, &fence, ring->idx); | 582 | r = radeon_fence_emit(rdev, &fence, ring->idx); |
| 587 | if (r) { | 583 | if (r) { |
| 588 | radeon_ring_unlock_undo(rdev, ring); | 584 | radeon_ring_unlock_undo(rdev, ring); |
| 589 | radeon_semaphore_free(rdev, &sem, NULL); | 585 | radeon_sync_free(rdev, &sync, NULL); |
| 590 | return ERR_PTR(r); | 586 | return ERR_PTR(r); |
| 591 | } | 587 | } |
| 592 | 588 | ||
| 593 | radeon_ring_unlock_commit(rdev, ring, false); | 589 | radeon_ring_unlock_commit(rdev, ring, false); |
| 594 | radeon_semaphore_free(rdev, &sem, fence); | 590 | radeon_sync_free(rdev, &sync, fence); |
| 595 | 591 | ||
| 596 | return fence; | 592 | return fence; |
| 597 | } | 593 | } |
| @@ -904,25 +900,21 @@ void cik_sdma_vm_pad_ib(struct radeon_ib *ib) | |||
| 904 | * Update the page table base and flush the VM TLB | 900 | * Update the page table base and flush the VM TLB |
| 905 | * using sDMA (CIK). | 901 | * using sDMA (CIK). |
| 906 | */ | 902 | */ |
| 907 | void cik_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm) | 903 | void cik_dma_vm_flush(struct radeon_device *rdev, struct radeon_ring *ring, |
| 904 | unsigned vm_id, uint64_t pd_addr) | ||
| 908 | { | 905 | { |
| 909 | struct radeon_ring *ring = &rdev->ring[ridx]; | ||
| 910 | |||
| 911 | if (vm == NULL) | ||
| 912 | return; | ||
| 913 | |||
| 914 | radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); | 906 | radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); |
| 915 | if (vm->id < 8) { | 907 | if (vm_id < 8) { |
| 916 | radeon_ring_write(ring, (VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm->id << 2)) >> 2); | 908 | radeon_ring_write(ring, (VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm_id << 2)) >> 2); |
| 917 | } else { | 909 | } else { |
| 918 | radeon_ring_write(ring, (VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((vm->id - 8) << 2)) >> 2); | 910 | radeon_ring_write(ring, (VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + ((vm_id - 8) << 2)) >> 2); |
| 919 | } | 911 | } |
| 920 | radeon_ring_write(ring, vm->pd_gpu_addr >> 12); | 912 | radeon_ring_write(ring, pd_addr >> 12); |
| 921 | 913 | ||
| 922 | /* update SH_MEM_* regs */ | 914 | /* update SH_MEM_* regs */ |
| 923 | radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); | 915 | radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); |
| 924 | radeon_ring_write(ring, SRBM_GFX_CNTL >> 2); | 916 | radeon_ring_write(ring, SRBM_GFX_CNTL >> 2); |
| 925 | radeon_ring_write(ring, VMID(vm->id)); | 917 | radeon_ring_write(ring, VMID(vm_id)); |
| 926 | 918 | ||
| 927 | radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); | 919 | radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); |
| 928 | radeon_ring_write(ring, SH_MEM_BASES >> 2); | 920 | radeon_ring_write(ring, SH_MEM_BASES >> 2); |
| @@ -945,11 +937,11 @@ void cik_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm | |||
| 945 | radeon_ring_write(ring, VMID(0)); | 937 | radeon_ring_write(ring, VMID(0)); |
| 946 | 938 | ||
| 947 | /* flush HDP */ | 939 | /* flush HDP */ |
| 948 | cik_sdma_hdp_flush_ring_emit(rdev, ridx); | 940 | cik_sdma_hdp_flush_ring_emit(rdev, ring->idx); |
| 949 | 941 | ||
| 950 | /* flush TLB */ | 942 | /* flush TLB */ |
| 951 | radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); | 943 | radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000)); |
| 952 | radeon_ring_write(ring, VM_INVALIDATE_REQUEST >> 2); | 944 | radeon_ring_write(ring, VM_INVALIDATE_REQUEST >> 2); |
| 953 | radeon_ring_write(ring, 1 << vm->id); | 945 | radeon_ring_write(ring, 1 << vm_id); |
| 954 | } | 946 | } |
| 955 | 947 | ||
