1 files changed, 106 insertions, 14 deletions

diff --git a/drivers/gpu/drm/radeon/cik_sdma.c b/drivers/gpu/drm/radeon/cik_sdma.c
index d08b83c6267b..1ecb3f1070e3 100644
--- a/drivers/gpu/drm/radeon/cik_sdma.c
+++ b/drivers/gpu/drm/radeon/cik_sdma.c
@@ -52,6 +52,75 @@ u32 cik_gpu_check_soft_reset(struct radeon_device *rdev);
  */
 
 /**
+ * cik_sdma_get_rptr - get the current read pointer
+ *
+ * @rdev: radeon_device pointer
+ * @ring: radeon ring pointer
+ *
+ * Get the current rptr from the hardware (CIK+).
+ */
+uint32_t cik_sdma_get_rptr(struct radeon_device *rdev,
+                           struct radeon_ring *ring)
+{
+        u32 rptr, reg;
+
+        if (rdev->wb.enabled) {
+                rptr = rdev->wb.wb[ring->rptr_offs/4];
+        } else {
+                if (ring->idx == R600_RING_TYPE_DMA_INDEX)
+                        reg = SDMA0_GFX_RB_RPTR + SDMA0_REGISTER_OFFSET;
+                else
+                        reg = SDMA0_GFX_RB_RPTR + SDMA1_REGISTER_OFFSET;
+
+                rptr = RREG32(reg);
+        }
+
+        return (rptr & 0x3fffc) >> 2;
+}
+
+/**
+ * cik_sdma_get_wptr - get the current write pointer
+ *
+ * @rdev: radeon_device pointer
+ * @ring: radeon ring pointer
+ *
+ * Get the current wptr from the hardware (CIK+).
+ */
+uint32_t cik_sdma_get_wptr(struct radeon_device *rdev,
+                           struct radeon_ring *ring)
+{
+        u32 reg;
+
+        if (ring->idx == R600_RING_TYPE_DMA_INDEX)
+                reg = SDMA0_GFX_RB_WPTR + SDMA0_REGISTER_OFFSET;
+        else
+                reg = SDMA0_GFX_RB_WPTR + SDMA1_REGISTER_OFFSET;
+
+        return (RREG32(reg) & 0x3fffc) >> 2;
+}
+
+/**
+ * cik_sdma_set_wptr - commit the write pointer
+ *
+ * @rdev: radeon_device pointer
+ * @ring: radeon ring pointer
+ *
+ * Write the wptr back to the hardware (CIK+).
+ */
+void cik_sdma_set_wptr(struct radeon_device *rdev,
+                       struct radeon_ring *ring)
+{
+        u32 reg;
+
+        if (ring->idx == R600_RING_TYPE_DMA_INDEX)
+                reg = SDMA0_GFX_RB_WPTR + SDMA0_REGISTER_OFFSET;
+        else
+                reg = SDMA0_GFX_RB_WPTR + SDMA1_REGISTER_OFFSET;
+
+        WREG32(reg, (ring->wptr << 2) & 0x3fffc);
+}
+
+/**
  * cik_sdma_ring_ib_execute - Schedule an IB on the DMA engine
  *
  * @rdev: radeon_device pointer
@@ -88,6 +157,35 @@ void cik_sdma_ring_ib_execute(struct radeon_device *rdev,
 }
 
 /**
+ * cik_sdma_hdp_flush_ring_emit - emit an hdp flush on the DMA ring
+ *
+ * @rdev: radeon_device pointer
+ * @ridx: radeon ring index
+ *
+ * Emit an hdp flush packet on the requested DMA ring.
+ */
+static void cik_sdma_hdp_flush_ring_emit(struct radeon_device *rdev,
+                                         int ridx)
+{
+        struct radeon_ring *ring = &rdev->ring[ridx];
+        u32 extra_bits = (SDMA_POLL_REG_MEM_EXTRA_OP(1) |
+                          SDMA_POLL_REG_MEM_EXTRA_FUNC(3)); /* == */
+        u32 ref_and_mask;
+
+        if (ridx == R600_RING_TYPE_DMA_INDEX)
+                ref_and_mask = SDMA0;
+        else
+                ref_and_mask = SDMA1;
+
+        radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0, extra_bits));
+        radeon_ring_write(ring, GPU_HDP_FLUSH_DONE);
+        radeon_ring_write(ring, GPU_HDP_FLUSH_REQ);
+        radeon_ring_write(ring, ref_and_mask); /* reference */
+        radeon_ring_write(ring, ref_and_mask); /* mask */
+        radeon_ring_write(ring, (0xfff << 16) | 10); /* retry count, poll interval */
+}
+
+/**
  * cik_sdma_fence_ring_emit - emit a fence on the DMA ring
  *
  * @rdev: radeon_device pointer
@@ -111,12 +209,7 @@ void cik_sdma_fence_ring_emit(struct radeon_device *rdev,
         /* generate an interrupt */
         radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_TRAP, 0, 0));
         /* flush HDP */
-        /* We should be using the new POLL_REG_MEM special op packet here
-         * but it causes sDMA to hang sometimes
-         */
-        radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
-        radeon_ring_write(ring, HDP_MEM_COHERENCY_FLUSH_CNTL >> 2);
-        radeon_ring_write(ring, 0);
+        cik_sdma_hdp_flush_ring_emit(rdev, fence->ring);
 }
 
 /**
@@ -157,7 +250,9 @@ static void cik_sdma_gfx_stop(struct radeon_device *rdev)
         u32 rb_cntl, reg_offset;
         int i;
 
-        radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
+        if ((rdev->asic->copy.copy_ring_index == R600_RING_TYPE_DMA_INDEX) ||
+            (rdev->asic->copy.copy_ring_index == CAYMAN_RING_TYPE_DMA1_INDEX))
+                radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size);
 
         for (i = 0; i < 2; i++) {
                 if (i == 0)
@@ -288,7 +383,9 @@ static int cik_sdma_gfx_resume(struct radeon_device *rdev)
                 }
         }
 
-        radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
+        if ((rdev->asic->copy.copy_ring_index == R600_RING_TYPE_DMA_INDEX) ||
+            (rdev->asic->copy.copy_ring_index == CAYMAN_RING_TYPE_DMA1_INDEX))
+                radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size);
 
         return 0;
 }
@@ -747,12 +844,7 @@ void cik_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm
         radeon_ring_write(ring, VMID(0));
 
         /* flush HDP */
-        /* We should be using the new POLL_REG_MEM special op packet here
-         * but it causes sDMA to hang sometimes
-         */
-        radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
-        radeon_ring_write(ring, HDP_MEM_COHERENCY_FLUSH_CNTL >> 2);
-        radeon_ring_write(ring, 0);
+        cik_sdma_hdp_flush_ring_emit(rdev, ridx);
 
         /* flush TLB */
         radeon_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));