1 files changed, 14 insertions, 4 deletions

diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c
index 69a00d64716e..dcd4518a9b08 100644
--- a/drivers/gpu/drm/radeon/cik.c
+++ b/drivers/gpu/drm/radeon/cik.c
@@ -80,6 +80,7 @@ extern int sumo_rlc_init(struct radeon_device *rdev);
 extern void si_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
 extern void si_rlc_reset(struct radeon_device *rdev);
 extern void si_init_uvd_internal_cg(struct radeon_device *rdev);
+static u32 cik_get_cu_active_bitmap(struct radeon_device *rdev, u32 se, u32 sh);
 extern int cik_sdma_resume(struct radeon_device *rdev);
 extern void cik_sdma_enable(struct radeon_device *rdev, bool enable);
 extern void cik_sdma_fini(struct radeon_device *rdev);
@@ -3257,7 +3258,7 @@ static void cik_gpu_init(struct radeon_device *rdev)
         u32 mc_shared_chmap, mc_arb_ramcfg;
         u32 hdp_host_path_cntl;
         u32 tmp;
-        int i, j;
+        int i, j, k;
 
         switch (rdev->family) {
         case CHIP_BONAIRE:
@@ -3446,6 +3447,15 @@ static void cik_gpu_init(struct radeon_device *rdev)
                      rdev->config.cik.max_sh_per_se,
                      rdev->config.cik.max_backends_per_se);
 
+        for (i = 0; i < rdev->config.cik.max_shader_engines; i++) {
+                for (j = 0; j < rdev->config.cik.max_sh_per_se; j++) {
+                        for (k = 0; k < rdev->config.cik.max_cu_per_sh; k++) {
+                                rdev->config.cik.active_cus +=
+                                        hweight32(cik_get_cu_active_bitmap(rdev, i, j));
+                        }
+                }
+        }
+
         /* set HW defaults for 3D engine */
         WREG32(CP_MEQ_THRESHOLDS, MEQ1_START(0x30) | MEQ2_START(0x60));
 
@@ -3698,7 +3708,7 @@ bool cik_semaphore_ring_emit(struct radeon_device *rdev,
         unsigned sel = emit_wait ? PACKET3_SEM_SEL_WAIT : PACKET3_SEM_SEL_SIGNAL;
 
         radeon_ring_write(ring, PACKET3(PACKET3_MEM_SEMAPHORE, 1));
-        radeon_ring_write(ring, addr & 0xffffffff);
+        radeon_ring_write(ring, lower_32_bits(addr));
         radeon_ring_write(ring, (upper_32_bits(addr) & 0xffff) | sel);
 
         return true;
@@ -3818,7 +3828,7 @@ void cik_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
                         radeon_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
                         radeon_ring_write(ring, WRITE_DATA_DST_SEL(1));
                         radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc);
-                        radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xffffffff);
+                        radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr));
                         radeon_ring_write(ring, next_rptr);
                 }
 
@@ -5446,7 +5456,7 @@ static int cik_pcie_gart_enable(struct radeon_device *rdev)
                (u32)(rdev->dummy_page.addr >> 12));
         WREG32(VM_CONTEXT1_CNTL2, 4);
         WREG32(VM_CONTEXT1_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(1) |
-                                PAGE_TABLE_BLOCK_SIZE(RADEON_VM_BLOCK_SIZE - 9) |
+                                PAGE_TABLE_BLOCK_SIZE(radeon_vm_block_size - 9) |
                                 RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT |
                                 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT |
                                 DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT |