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path: root/drivers/gpu/drm/radeon/cik.c
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Diffstat (limited to 'drivers/gpu/drm/radeon/cik.c')
-rw-r--r--drivers/gpu/drm/radeon/cik.c10
1 files changed, 7 insertions, 3 deletions
diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c
index e6419ca7cd37..bbb17841a9e5 100644
--- a/drivers/gpu/drm/radeon/cik.c
+++ b/drivers/gpu/drm/radeon/cik.c
@@ -3046,7 +3046,7 @@ static u32 cik_create_bitmask(u32 bit_width)
3046} 3046}
3047 3047
3048/** 3048/**
3049 * cik_select_se_sh - select which SE, SH to address 3049 * cik_get_rb_disabled - computes the mask of disabled RBs
3050 * 3050 *
3051 * @rdev: radeon_device pointer 3051 * @rdev: radeon_device pointer
3052 * @max_rb_num: max RBs (render backends) for the asic 3052 * @max_rb_num: max RBs (render backends) for the asic
@@ -4134,8 +4134,11 @@ static void cik_cp_compute_enable(struct radeon_device *rdev, bool enable)
4134{ 4134{
4135 if (enable) 4135 if (enable)
4136 WREG32(CP_MEC_CNTL, 0); 4136 WREG32(CP_MEC_CNTL, 0);
4137 else 4137 else {
4138 WREG32(CP_MEC_CNTL, (MEC_ME1_HALT | MEC_ME2_HALT)); 4138 WREG32(CP_MEC_CNTL, (MEC_ME1_HALT | MEC_ME2_HALT));
4139 rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX].ready = false;
4140 rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX].ready = false;
4141 }
4139 udelay(50); 4142 udelay(50);
4140} 4143}
4141 4144
@@ -7902,7 +7905,8 @@ int cik_resume(struct radeon_device *rdev)
7902 /* init golden registers */ 7905 /* init golden registers */
7903 cik_init_golden_registers(rdev); 7906 cik_init_golden_registers(rdev);
7904 7907
7905 radeon_pm_resume(rdev); 7908 if (rdev->pm.pm_method == PM_METHOD_DPM)
7909 radeon_pm_resume(rdev);
7906 7910
7907 rdev->accel_working = true; 7911 rdev->accel_working = true;
7908 r = cik_startup(rdev); 7912 r = cik_startup(rdev);