diff options
Diffstat (limited to 'drivers/gpu/drm/radeon/atombios_crtc.c')
-rw-r--r-- | drivers/gpu/drm/radeon/atombios_crtc.c | 31 |
1 files changed, 23 insertions, 8 deletions
diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c index a9338c85630f..daa4dd375ab1 100644 --- a/drivers/gpu/drm/radeon/atombios_crtc.c +++ b/drivers/gpu/drm/radeon/atombios_crtc.c | |||
@@ -559,7 +559,7 @@ static u32 atombios_adjust_pll(struct drm_crtc *crtc, | |||
559 | u32 adjusted_clock = mode->clock; | 559 | u32 adjusted_clock = mode->clock; |
560 | int encoder_mode = atombios_get_encoder_mode(encoder); | 560 | int encoder_mode = atombios_get_encoder_mode(encoder); |
561 | u32 dp_clock = mode->clock; | 561 | u32 dp_clock = mode->clock; |
562 | int bpc = radeon_get_monitor_bpc(connector); | 562 | int bpc = radeon_crtc->bpc; |
563 | bool is_duallink = radeon_dig_monitor_is_duallink(encoder, mode->clock); | 563 | bool is_duallink = radeon_dig_monitor_is_duallink(encoder, mode->clock); |
564 | 564 | ||
565 | /* reset the pll flags */ | 565 | /* reset the pll flags */ |
@@ -1176,7 +1176,7 @@ static int dce4_crtc_do_set_base(struct drm_crtc *crtc, | |||
1176 | evergreen_tiling_fields(tiling_flags, &bankw, &bankh, &mtaspect, &tile_split); | 1176 | evergreen_tiling_fields(tiling_flags, &bankw, &bankh, &mtaspect, &tile_split); |
1177 | 1177 | ||
1178 | /* Set NUM_BANKS. */ | 1178 | /* Set NUM_BANKS. */ |
1179 | if (rdev->family >= CHIP_BONAIRE) { | 1179 | if (rdev->family >= CHIP_TAHITI) { |
1180 | unsigned tileb, index, num_banks, tile_split_bytes; | 1180 | unsigned tileb, index, num_banks, tile_split_bytes; |
1181 | 1181 | ||
1182 | /* Calculate the macrotile mode index. */ | 1182 | /* Calculate the macrotile mode index. */ |
@@ -1194,13 +1194,14 @@ static int dce4_crtc_do_set_base(struct drm_crtc *crtc, | |||
1194 | return -EINVAL; | 1194 | return -EINVAL; |
1195 | } | 1195 | } |
1196 | 1196 | ||
1197 | num_banks = (rdev->config.cik.macrotile_mode_array[index] >> 6) & 0x3; | 1197 | if (rdev->family >= CHIP_BONAIRE) |
1198 | num_banks = (rdev->config.cik.macrotile_mode_array[index] >> 6) & 0x3; | ||
1199 | else | ||
1200 | num_banks = (rdev->config.si.tile_mode_array[index] >> 20) & 0x3; | ||
1198 | fb_format |= EVERGREEN_GRPH_NUM_BANKS(num_banks); | 1201 | fb_format |= EVERGREEN_GRPH_NUM_BANKS(num_banks); |
1199 | } else { | 1202 | } else { |
1200 | /* SI and older. */ | 1203 | /* NI and older. */ |
1201 | if (rdev->family >= CHIP_TAHITI) | 1204 | if (rdev->family >= CHIP_CAYMAN) |
1202 | tmp = rdev->config.si.tile_config; | ||
1203 | else if (rdev->family >= CHIP_CAYMAN) | ||
1204 | tmp = rdev->config.cayman.tile_config; | 1205 | tmp = rdev->config.cayman.tile_config; |
1205 | else | 1206 | else |
1206 | tmp = rdev->config.evergreen.tile_config; | 1207 | tmp = rdev->config.evergreen.tile_config; |
@@ -1773,6 +1774,20 @@ static int radeon_atom_pick_pll(struct drm_crtc *crtc) | |||
1773 | return ATOM_PPLL1; | 1774 | return ATOM_PPLL1; |
1774 | DRM_ERROR("unable to allocate a PPLL\n"); | 1775 | DRM_ERROR("unable to allocate a PPLL\n"); |
1775 | return ATOM_PPLL_INVALID; | 1776 | return ATOM_PPLL_INVALID; |
1777 | } else if (ASIC_IS_DCE41(rdev)) { | ||
1778 | /* Don't share PLLs on DCE4.1 chips */ | ||
1779 | if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) { | ||
1780 | if (rdev->clock.dp_extclk) | ||
1781 | /* skip PPLL programming if using ext clock */ | ||
1782 | return ATOM_PPLL_INVALID; | ||
1783 | } | ||
1784 | pll_in_use = radeon_get_pll_use_mask(crtc); | ||
1785 | if (!(pll_in_use & (1 << ATOM_PPLL1))) | ||
1786 | return ATOM_PPLL1; | ||
1787 | if (!(pll_in_use & (1 << ATOM_PPLL2))) | ||
1788 | return ATOM_PPLL2; | ||
1789 | DRM_ERROR("unable to allocate a PPLL\n"); | ||
1790 | return ATOM_PPLL_INVALID; | ||
1776 | } else if (ASIC_IS_DCE4(rdev)) { | 1791 | } else if (ASIC_IS_DCE4(rdev)) { |
1777 | /* in DP mode, the DP ref clock can come from PPLL, DCPLL, or ext clock, | 1792 | /* in DP mode, the DP ref clock can come from PPLL, DCPLL, or ext clock, |
1778 | * depending on the asic: | 1793 | * depending on the asic: |
@@ -1800,7 +1815,7 @@ static int radeon_atom_pick_pll(struct drm_crtc *crtc) | |||
1800 | if (pll != ATOM_PPLL_INVALID) | 1815 | if (pll != ATOM_PPLL_INVALID) |
1801 | return pll; | 1816 | return pll; |
1802 | } | 1817 | } |
1803 | } else if (!ASIC_IS_DCE41(rdev)) { /* Don't share PLLs on DCE4.1 chips */ | 1818 | } else { |
1804 | /* use the same PPLL for all monitors with the same clock */ | 1819 | /* use the same PPLL for all monitors with the same clock */ |
1805 | pll = radeon_get_shared_nondp_ppll(crtc); | 1820 | pll = radeon_get_shared_nondp_ppll(crtc); |
1806 | if (pll != ATOM_PPLL_INVALID) | 1821 | if (pll != ATOM_PPLL_INVALID) |